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mos integrated circuit m pd17201a, 17207 description the m pd17201a, 17207 is a 4-bit single-chip microcontroller, used for infrared remote control transmitters, which in-tegrates an lcd controller/driver, a/d converter, and remote controller carrier generator circuit on a single chip. for the cpu, this microcontroller employs the 17k architecture of the general-purpose register method, and it can directly execute operations between data memory addresses which would have been conventionally executed by an accumulator. in addition, all the instructions are 16-bit, 1-word instructions, enabling efficient programming. a one-time prom model, m pd17p207, to which data can be written only once is also available. this one-time prom model is useful for program evaluation of the m pd17201a or 17207. detalied functionins are described in the following manual. be sure to read this manual when designing your system. m pd172xx subseries users manual: ieu-1317 features ? 17k architecture : general-purpose register method ? program memory (rom) : 3072 x 16 bits ( m pd17201a) 4096 x 16 bits ( m pd17207) ? data memory (ram) : 336 x 4 bits (including lcd register 36 4 bits) ? infrared remote controller carrier generator (rem output) ? lcd controller/driver : up to 136 segments can be displayed common pins : 4 (2 can be used as segment pins) segment pins : 34 voltage booster circuit for driving lcd : lcd drive voltage can be adjusted from 2.4 to 5.4 v with external resistor ? 8-bit a/d converter : 4 channels (successive approximation method in software) ? 8-bit timer : 1 channel ? watch timer/watchdog timer : 1 channel (wdout output) ? 3-line serial interface : 1 channel ? external interrupt pin (int) : 1 ? i/o pin : 20 (including int) ? instruction execution time : 4 m s (main clock: f x = 4 mhz) 488 m s (subclock: f xt = 32.768 khz) ? supply voltage : v dd = 2.2 to 5.5 v (main clock : f x = 4 mhz) :v dd = 2.0 to 5.5 v (subclock : f xt = 32.768 khz) unless otherwise specified, the m pd17207 is treated as the representative model throughout this documents. document no. u11778ej5v0ds00 (5th edition) (previous no. ic-2773) date published november 1996 p printed in japan the information in this document is subject to change without notice. the mark shows major revised points. 4-bit single-chip microcontroller with lcd controller/driver and a/d converter for infrared remote control transmitters 1991 data sheet
m pd17201a, 17207 2 applications ? infrared remote controller for air conditioner ? infrared remote controller with lcd display ordering information part number pakcage m pd17201agf-xxx-3b9 80-pin plastic qfp (14 mm x 20 mm) m pd17207gf-xxx-3b9 80-pin plastic qfp (14 mm x 20 mm) remark xxx indicates the rom code number.
m pd17201a, 17207 3 table of contents 1. pin configuration (top view) ............................................................................................. 6 2. block diagram ......................................................................................................................... 8 3. pins functions .......................................................................................................................... 9 3.1 pin identification ........................................................................................................................... 9 3.2 equivalent circuits of pins ..................................................................................................... 11 3.3 processing of unused pins ...................................................................................................... 12 3.4 notes on using reset and int pins ........................................................................................ 13 4. memory space ........................................................................................................................... 14 4.1 program counter (pc) ................................................................................................................ 14 4.2 program memory (rom) .............................................................................................................. 14 4.3 stack ....................................................................................................................... ............................ 15 4.4 data memory (ram) ........................................................................................................................ 17 4.5 register file (rf) ........................................................................................................................... 25 5. ports ............................................................................................................................... ............. 28 5.1 port 0a ..................................................................................................................... .......................... 28 5.2 port 0b ..................................................................................................................... .......................... 28 5.3 port 0c ..................................................................................................................... .......................... 28 5.4 port 0d ..................................................................................................................... .......................... 28 5.5 port 1a ..................................................................................................................... .......................... 29 5.6 int pin ............................................................................................................................... ................... 29 5.7 port control register .............................................................................................................. 30 6. clock generator circuit .................................................................................................... 33 6.1 switching system clock ............................................................................................................ 34 6.2 main clock oscillation control function ....................................................................... 34 7. 8-bit timer and remote controller carrier generator circuit .................... 35 7.1 configuration of the 8-bit timer (with modulo function) ......................................... 35 7.2 function of the 8-bit timer (with modulo function) .................................................... 37 7.3 remote controller carrier generator ........................................................................... 38 8. watch timer/watchdog timer ............................................................................................ 43 8.1 configuration of watch timer/watchdog timer ............................................................ 43 8.2 function of watch timer/watchdog timer ........................................................................ 44 8.3 watchdog timer operation timing ........................................................................................ 45
m pd17201a, 17207 4 9. a/d converter .......................................................................................................................... 46 9.1 configuration of a/d converter ........................................................................................... 46 9.2 function of a/d converter ...................................................................................................... 47 9.3 control registers of a/d converter ................................................................................. 48 9.4 operation in a/d conversion mode ........................................................................................ 50 9.5 operation in compare mode ..................................................................................................... 52 10. serial interface ..................................................................................................................... 54 10.1 serial interface function ........................................................................................................ 54 10.2 serial interface operation ...................................................................................................... 54 11. lcd controller/driver ........................................................................................................ 58 11.1 configuration of lcd controller/driver ........................................................................ 58 11.2 functions of lcd controller/driver .................................................................................. 59 11.3 display mode register ................................................................................................................ 59 11.4 lcd register ............................................................................................................................... ..... 63 11.5 segment signals and common signals ................................................................................ 67 11.6 voltage booster circuit for lcd driver .......................................................................... 70 12. interrupt functions ............................................................................................................ 72 12.1 interrupt sources ....................................................................................................................... 72 12.2 hardware of interrupt control circuit .......................................................................... 72 12.3 interrupt sequence .................................................................................................................... 77 13. standby functions ................................................................................................................. 78 13.1 halt mode ............................................................................................................................... ........... 78 13.2 conditions of executing an halt instruction ................................................................ 80 13.3 stop mode ............................................................................................................................... .......... 81 13.4 conditions of executing an halt instruction ................................................................ 82 14. reset ............................................................................................................................... .............. 83 14.1 reset by reset signal input .................................................................................................... 83 14.2 reset by watchdog timer (reset and wdout pins connected) ................................ 83 14.3 reset by stack pointer (reset and wdout pins connected) .................................... 83 15. assembler reserved words .............................................................................................. 85 15.1 mask option directives .............................................................................................................. 85 15.2 reserved symbols ........................................................................................................................ 86 16. instruction set ........................................................................................................................ 94 16.1 outline of instruction sets .................................................................................................... 94 16.2 legend ............................................................................................................................... ................. 95 16.3 list of instruction sets ............................................................................................................ 96 16.4 assembler (as17k) embedded macroinstructions ......................................................... 98 17. electrical specifications .................................................................................................. 99 18. performance curve (reference value) ...................................................................... 106
m pd17201a, 17207 5 19. example of application circuit ....................................................................................... 110 20. package drawings .................................................................................................................. 111 21. recommended soldering conditions ............................................................................ 113 appendix a. differences between m pd17p207 and m pd17201a/17207 .......................... 114 appendix b. functional comparison of m pd17201a/17207 related products ...... 115 appendix c. development tools ............................................................................................. 116
m pd17201a, 17207 6 1. pin configuration (top view) 35 28 lcd 32 lcd 31 lcd 30 lcd 29 lcd 28 lcd 27 lcd 26 lcd 25 lcd 24 lcd 23 lcd 22 lcd 21 lcd 20 lcd 19 lcd 18 lcd 17 lcd 16 lcd 15 lcd 14 lcd 13 lcd 12 lcd 11 lcd 10 lcd 9 x out x in v dd rem p1a 2 /si p1a 1 /so p1a 0 /sck p0d 3 p0d 2 p0d 1 /tmout p0d 0 /led p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 int lcd 33 lcd 34 /com 3 lcd 35 /com 2 com 1 com 0 capl caph v lcd2 v lcd1 v lcdc v lcd0 xt out xt in wdout v reg reset lcd 8 lcd 7 lcd 6 lcd 5 lcd 4 lcd 3 lcd 2 lcd 1 gnd lcd 0 v adc adc 0 adc 1 adc 2 adc 3 gnd adc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 74 72 71 68 67 66 65 25 31 33 37 38 39 40 pd17201agf-xxx-3b9 pd17207gf-xxx-3b9 26 27 29 30 32 34 36 79 78 77 76 75 73 70 69
m pd17201a, 17207 7 rem : remote controller transfer output reset : reset signal input sck : serial clock i/o si : serial data input so : serial data output tmout : timer output v adc : a/d converter power supply v dd : power supply v lcd0 -v lcd2 : lcd driver voltage output v lcdc : lcd driver reference voltage adjustment v reg : voltage regulator output wdout : overrun detection output x in , x out : main clock oscillator circuit xt in , xt out : subclock oscillator circuit pin name adc 0 -adc 3 : a/d converter input caph, capl : booster capacitor connection com 0 -com 3 : lcd common signal output gnd, gnd adc : ground int : external interrupt request signal input lcd 0 -lcd 35 : lcd segment signal output led : remote controller transfer display output p0a 0 -p0a 3 : i/o port p0b 0 -p0b 3 : i/o port p0c 0 -p0c 3 : i/o port p0d 0 -p0d 3 : i/o port p1a 0 -p1a 2 : i/o port
m pd17201a, 17207 8 2. block diagram p1a 0 /sck p1a 1 /so p1a 2 /si p0a 0 p0a 1 p0a 2 p0a 3 p0b 0 p0b 1 p0b 2 p0b 3 p0c 0 p0c 1 p0c 2 p0c 3 p0d 0 /led p0d 1 /tmout p0d 2 p0d 3 rem serial interface p1a p0a p0b p0c p0d carrier gene- rator ram 336 4 bits system reg. rom 4096 16 bits program counter stack 5 12 bits instruction decoder v reg v dd caph capl v lcd0 v lcd1 v lcd2 v lcdc gmd lcd 0 lcd 1 lcd 2 lcd 3 lcd 4 lcd 33 com 3 /lcd 34 com 2 /lcd 35 com 1 com 0 cpu clock clock stop cpu clock int v adc adc 0 adc 1 adc 2 adc 3 gnd adc reset a/d converter interrupt controller lcd controller x in x out xt in xt out watch timer divider main clock subclock rf ( pd17207) 3072 16 bits ( pd17201a) timer/ counter alu power supply circuit wdout
m pd17201a, 17207 9 3. pins functions 3.1 pin identification pin no. symbol function output type on reset 76 com 0 cmos, C 77 com 1 push-pull 78 lcd 35 /com 2 79 lcd 34 /com 3 80 lcd 33 1 lcd 32 || 32 lcd 1 34 lcd 0 33 gnd CC 35 v adc CC 36 adc 0 CC || 39 adc 3 40 gnd adc CC 41 int C input 42 p0a 0 cmos, input || push-pull 45 p0a 3 46 p0b 0 n-channel, input || open-drain 49 p0b 3 50 p0c 0 n-channel, input || open-drain 53 p0c 3 54 p0d 0 /led cmos, input 55 p0d 1 /tmout push-pull 56 p0d 2 57 p0d 3 common/segment signal outputs of the lcd driver. these common and segment signal outputs are selected by lcdmd3 to lcdmd0 of the register file. ? com 0 to com 3 ? common signal outputs of the lcd driver ? lcd 35 to lcd 0 ? segment signal outputs of the lcd driver device ground positive power supply of the a/d converter (v adc should be equal to v dd .) analog inputs of the a/d converter (8-bit resolution) ground of the a/d converter external interrupt request signal (input). the interrupt request is generated at the rising edge of this signal. 4-bit i/o port (enabling setting of inputs or outputs in 4-bit units) (grouped i/o). each of these pins has a pull-up resistor. 4-bit i/o port (enabling setting of inputs or outputs in 4-bit units). (grouped i/o). 4-bit i/o port (enabling setting of inputs or outputs in 4-bit units). (grouped i/o). port 0d/led output or port 0d/8-bit timer output. p0d 0 and led outputs are switched by nrzen of the register file. p0d1 and 8-bit timer outputs are switched by tmoe of the register file. ? p0d 0 to p0d 3 ? 4-bit i/o port ? enabling setting of inputs or outputs of each bit (bitwise i/o) ? led ? outputs nrz signal in synchronization with infrared remote controller signal (rem) ? outputs high level while remote controller carrier is output from rem pin ? tmout ? output of the 8-bit timer (to be contd)
m pd17201a, 17207 10 (contd) pin no. symbol function output type on reset 58 p1a 0 /sck port 1a or serial interface. cmos, input 59 p1a 1 /so port 1a and serial interface are switched by sioen of the register file. push-pull 60 p1a 2 /si ? p1a 0 to p1a 2 ? 3-bit i/o port ? enabling setting of inputs or outputs of 3 bits (grouped i/o). ? sck, so, si ? sck : serial clock i/o ? so : serial data output ? si : serial data input 61 rem signal output to an infrared remote controller. cmos, low-level active-high output. push-pull output 62 v dd positive power supply C C 63 x in these pins are connected to a 4-mhz ceramic or crystal oscillator C (oscillation 64 x out for main clock oscillation. stops) 65 reset system reset input. C input system is reset when low level is input to this pin. while this pin is low, oscillation of main clock is stopped. a pull-up resistor can be connected by mask option. 66 v reg output of the voltage regulator for the subclock oscillation circuit. C C connect external 0.1- m f capacitor to this pin when using the subclock. 67 wdout output for detection of a program overrun. n-ch high- this pin outputs a low level when an overflow in the watchdog timer open drain impedance or an overflow/underflow in the stack is detected. connect this pin to the reset pin 68 xt in these pins are connected to a 32.768-khz crystal oscillator for C (oscillates) 69 xt out subclock oscillation. 71 v lcdc input to regulate the reference voltage to lcd driver. C C 70 v lcd0 reference voltage outputs to lcd driver. C C 72 v lcd1 ?v lcd0 : reference voltage output 73 v lcd2 ?v lcd1 : doubler output (two times the reference voltage) ?v lcd2 : tripler output (three times the reference voltage) 74 caph these pins are connected to a capacitor to boost the lcd drive C C 75 capl voltage.
m pd17201a, 17207 11 3.2 equivalent circuits of pins the followings are equivalent circuits (partially simplified) of the respective pins of the m pd17207. (1) p0a (4) p0d, p1a (2) p0b (5) reset (3) p0c (6) int v dd v dd output latch p-ch n-ch data output disable selector input buffer v dd output latch p-ch n-ch data output disable selector input buffer output latch n-ch data output disable input buffer input buffer (mask option) v dd input buffer output latch n-ch data output disable selector input buffer schmitt trigger input with hysteresis characteristics schmitt trigger input with hysteresis characteristics
m pd17201a, 17207 12 3.3 processing of unused pins process unused pins as follows: table 3-1 processing of unused pins (a) port pins pin name recommended processing of unused pins internally externally input mode p0a (connect pull-up resistor.) open. p0c C directly connect to gnd. p0d, p1a C connect each pin to v dd or gnd via resistor note . output mode p0a (cmos port) outputs high level. open. p0d, p1a (cmos port) C p0b, p0c (n-ch open-drain port) outputs low level. note when pulling this pin up (connecting the pin to v dd via resistor) or down (connect the pin to gnd via resistor), exercise care not to decrease the drive capability or increase the power consumption of the port. when a high resistance is used for pulling up or down, make sure that noise is not superimposed on the pin. (b) pins other than port pins pin name i/o format recommended processing of unused pin adc 0 -adc 3 input directly connect to gnd. caph, capl output open com 0 , com 1 , com 2 /lcd 35 , com 3 /lcd 34 output open int note input directly connect to gnd. lcd 0 -lcd 33 output open rem output open v adc C directly connect to v dd . v lcd0 -v lcd2 output open v lcdc C directly connect to v dd or v lcd0 . wdout output directly connect to gnd. x in , xt in input directly connect to gnd. x out C directly connect to v dd . xt out C directly connect to v reg . note because the int pin is also used as a test mode setting pin, directly connect this pin to gnd when it is not used. cautions 1. it is recommended to fix the input or output mode and the output level of the pin by repeatedly setting them in each loop of the program. 2. stop the voltage booster circuit by using the display mode register when the lcd driver/ controller is not in use.
m pd17201a, 17207 13 3.4 notes on using reset and int pins in addition to the functions shown in 3.1 pin identification, the reset and int pins also have a function to set a test mode (for ic testing) in which the internal operations of the m pd17207are tested. when a voltage higher than v dd is applied to either of these pins, the test mode is set. this means that, even during ordinary operation, the m pd17207 may be set in the test mode if a noise exceeding v dd is applied. for example, if the wiring length of the reset or int pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. ? connect diode with low v f between v dd ? connect capacitor between v dd and reset/int pin and reset/int pin v dd v dd v dd v dd reset, int diode with low v f reset, int
m pd17201a, 17207 14 4. memory space 4.1 program counter (pc) the program counter (pc) specifies an address of the program memory (rom). the program counter is a 12-bit binary counter as shown in fig. 4-1. its contents are initialized to address 0000h at reset. fig. 4-1 configuration of program counter 4.2 program memory (rom) the configuration of the program memory of the m pd17201a/17207 is as follows: part number capacity address m pd17201a 3072 x 16 bits 0000h-0bffh m pd17207 4096 x 16 bits 0000h-0fffh the program memory stores a program, interrupt vector table, and fixed data table. the program memory is addressed by the program counter. fig. 4-2 shows the program memory map. the entire range of the program memory can be addressed by the bd addr, br @ar, call @ar, movt dbf, and @ar instructions. note, however, that the subroutine entry addresses that can be specified by the call addr instruction are from 0000h to 07ffh. fig. 4-2 program memory map msb page pc pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 lsb address 0 0 0 0 h 0 0 0 1 h 0 0 0 2 h 0 0 0 3 h 0 0 0 4 h 0 7 f f h 0 b f f h 0 f f f h 16 bits reset start address serial interface interrupt vector watch timer interrupt vector external input (int) interrupt vector 8-bit timer interrupt vector ( pd17201a) page 0 page 1 subroutine entry addresses for call addr instruction branch addresses for br addr instruction branch addresses for br @ar instruction subroutine entry addresses for call @ar instruction table reference addresses for movt dbf, @ar instruction ( pd17207)
m pd17201a, 17207 15 fig. 4-4 stack pointer 4.3 stack a stack is a register to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is accepted. 4.3.1 stack configuration a stack consists of a stack pointer (a 3-bit binary counter), five 12-bit address stack registers (asr), and three 7-bit interrupt stack registers (intsk). refer to fig. 4-3 . the stack pointer specifies the addresses of the address stack registers. the value of this pointer is initialized to 5h at reset. when the value of the stack pointer is 6h or 7h, the wdout pin goes low. fig. 4-3 stack configuration address stack registers (asr) b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address stack register 1 address stack register 2 address stack register 3 address stack register 4 b 2 b 1 b 0 spb 2 spb 1 spb 0 stack pointer (sp) 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h 2h interrupt stack registers (intsk) banksk0 banksk1 banksk2 bcdsk0 bcdsk1 bcdsk2 cmpsk0 cmpsk1 cmpsk2 cysk0 cysk1 cysk2 zsk0 zsk1 zsk2 ixesk0 ixesk1 ixesk2 address stack register 0 undefined undefined undefined wdout pin goes low when the contents of the stack pointer are 6h-7h. rf: address 01 bit 3 bit 2 bit 1 bit 0 0101 0sp r/w initial value at reset read/write read = r, write = w
m pd17201a, 17207 16 4.3.2 function of stack the address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is accepted. it also stores the contents of the address registers (ars) when a stack manipulation instruction (push ar) is executed. the wdout pin goes low if a subroutine call or interrupt exceeding 5 levels is executed. the interrupt stack register (intsk) saves the contents of the bank register (bank) and program status word (psword) when an interrupt is accepted. the saved contents are restored when an interrupt return (reti) instruction is executed. intsk saves data each time an interrupt is accepted, but the data stored first is lost if more than 3 levels of interrupts occur . 4.3.3 stack pointer (sp) and interrupt stack pointer table 4-1 shows the operations of the stack pointer (sp). the stack pointer can take eight values, 0h-07. because there are only five stack registers available, however, the wdout pin goes low if the value of sp is 6 or greater . table 4-1 operations of stack pointer instruction value of stack pointer (sp) counter of interrupt stack register call addr call @ar movt dbf, @ar C1 0 (1st instruction cycle) push ar when interrupt is accepted C1 C1 ret retsk movt dbf, @ar +1 0 (2nd instruction cycle) pop ar reti +1 +1
m pd17201a, 17207 17 4.4. data memory (ram) data memory (random access memory) stores data for operations and control. it can be read-/write-accessed by instructions. 4.4.1 memory configuration figure 4-4 shows the configuration of the data memory (ram). the data memory consists of three banks: bank0, bank1, and bank2. in each bank, every 4 bits of data is assigned an address. the higher 3 bits of the address indicate a row address and the lower 4 bits of the address indicate a column address. for example, a data memory location indicated by row address 1h and column address 0ah is termed a data memory location at address 1ah. each address stores data of 4 bits (= a nibble). in addition, the data memory is divided into following six functional blocks: (1) system register (sysreg) a system register (sysreg) is resident on addresses 74h to 7fh (12 nibbles long) of each bank. in other nibbles, each bank has a system register at its addresses 74h to 7fh. (2) data buffer (dbf) a data buffer is resident on addresses 0ch to 0fh (4 nibbles long) of bank 0 of data memory. the reset value is 0320h. (3) general register (gr) a general register is resident on any row (16 nibbles long) of any bank of data memory. the row address of the general register is indicated by the general pointer (rp) in the system register (sysreg). (4) lcd segment data register (lcd register) a register sets the segment output data of lcd. refer to 11. lcd controller/driver . an lcd segment data register is resident on addresses 40h to 63h (36 nibbles long) of bank0 of data memory. (5) port register a port data register is resident on addresses 70h to 73h (12 nibbles) of each bank of data memory. however, addresses 71h to 73h of bank1 and addresses 70h to 73h of bank2 are assigned nothing. therefore, a port data register is substantially 4 nibbles long. the reset value is 0.
m pd17201a, 17207 18 (6) general-purpose data memory the general-purpose data memory area is an area of the data memory excluding the system register area, the lcd register area, and the port register area. this memory area has a total of 300 nibbles (76 nibbles in bank0 and 224 nibbles in bank1 and bank2). fig. 4-5 configuration of data memory 0123456789abcdef 0 1 2 3 4 5 6 7 bank 0 0123456789abcdef 0 1 2 3 4 5 6 7 bank 1 0123456789abcdef 0 1 2 3 4 5 6 7 bank 2 system register (sysreg) example : address 1ah in bank 0 system register (sysreg) system register (sysreg) row address row address row address column address data buffer (dbf) p0a p0b p0c p0d p1a lcd register
m pd17201a, 17207 19 4.4.2 system registers (sysreg) the system registers are registers that are directly related to control of the cpu. these registers are mapped to addresses 74h-7fh on the data memory and can be referenced regardless of bank specification. the system registers include the following registers: address registers (ar0-ar3) window register (wr) bank register (bank) memory pointer enable flag (mpe) memory pointers (mph, mpl) index registers (ixh, ixm, ixl) general register pointers (rph, rpl) program status word (psword) fig. 4-6 configuration of system register b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh ar 3 ar 2 ar 1 ar 0 wr bank ixh ixm ixl rph rpl psw mph mpl address register (ar) window register (wr) bank register (bank) data memory row address pointer (mp) index register (ix) general register pointer (rp) program status word (psword) 0000 00 00 00 m p e b c d c m p c yz i x e (rp) (ix) (mp) (bank) (ar) data bit symbol name address initial value at reset 0000000000000000 0000000000000000000000000000 undefined
m pd17201a, 17207 20 4.4.3 general register (gr) a general register is a 16-word register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) configuration of general register figure 4-7 shows the configuration of the general register. a general register occupies 16 nibbles (16 x 4 bits) on a selected row address of the data memory. the row address is selected by the general register pointer (rp) of the system register. the rp having five significant bits can point to any row address in the range of 0h to 7h of each bank (bank0 to bank2). (2) functions of the general register the general register enables an arithmetic operation and data transfer between the data memory and a selected general register by a single instruction. as a general register is a part of the data memory, you can say that the general register enables arithmetic operation and data transfer between two locations of the data memory. similarly, the general register can be accessed by a data memory manipulation instruction as it is a part of the data memory.
m pd17201a, 17207 21 fig. 4-7 configuration of general registers (rp) rph rpl b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 00000 0 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 0 01001 1 01010 2 01011 3 01100 4 01101 5 01110 6 01111 7 10000 0 10001 1 10010 2 10011 3 10100 4 10101 5 10110 6 10111 7 rp system registers port register general registers (16 nibbles) general register pointer bank0 bank1 bank2 port regis- ter column address general register settable range f i x e d t o 0 a s s i g n e d t o b c d f l a g ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? system registers system registers example: general registers when rp = 0000010b ? same system registers exist f i x e d t o 0 0 123 4 5678 9 a b cdef
m pd17201a, 17207 22 4.4.4 data buffer (dbf) the data buffer on the data memory is used for data transfer to and from peripheral hardware and for storage of data during table reference. (1) functions of the data buffer the data buffer has two major functions: a function to transfer to and from hardware and a function to read constant data from the program memory (for table reference). figure 4-8 shows the relationship between the data buffer and peripheral hardware. fig. 4-8 data buffer and peripheral hardware data buffer (dbf) internal bus program memory (rom) constant data peripheral address peripheral hardware serial interface (siosfr) 8-bit timer (tmc, tmm) carrier generator for remote controller a/d converter (adcr) address register (ar) 01 h 02 h 03 h/04 h 05h 40h
m pd17201a, 17207 23 table 4-2 relations between peripheral hardware and data buffer peripheral registers transferring data with data buffer peripheral hardware name symbol peripheral data buffer execution of put/get address used serial interface shift register siosfr 01h dbf0, dbf1 both put & get 8-bit timer 8-bit counter tmc 02h dbf0, dbf1 only get 8-bit modulo register tmm 02h dbf0, dbf1 only put remote controller nrz low-level period nrzltmm 03h dbf0, dbf1 both put & get carrier generator setting modulo register circuit nrz high-level period nrzhtmm 04h dbf0, dbf1 put (clears bits 2 and 3 setting modulo register of dbf1 to 0.) get (always clears bits 2 and 3 of dbf1 to 0.) a/d converter a/d converter internal adcr 05h dbf0, dbf1 both put & get reference voltage setting register address register address register ar 40h dbf0-dbf3 put (bits 0-3 of ar3 are dont care.) get (always clears bits 0-3 of ar3 to 0.) (2) table reference a movt instruction reads constant data from a specified location of the program memory (rom) and sets it in the data buffer. the function of the movt instruction is explained below. movt dbf,@ar: reads data from a program memory location pointed to by the address register (ar) and sets it in the data buffer (dbf). dbf 3 dbf 2 dbf 1 dbf 0 movt b 15 b 0 16 bits program memory (rom) data buffer dbf, @ ar
m pd17201a, 17207 24 (3) note on using data buffer when transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing put), and read-only peripheral registers (only when executing get) must be handled as follows: ? when device operates nothing changes even if data is written to the read-only register. if the unused address is read, an undefined value is read. nothing changes even if data is written to that address. ? using 17k series assembler an error occurs if an instruction is executed to read a write-only register. again, an error occurs if an instruction is executed to write data to a read-only register. an error also occurs if an instruction is executed to read or write an unused address. ? if an in-circuit emulator (ie-17k or ie-17k-et) is used (when instruction is executed for patch processing) an undefined value is read if an attempt is made to read the data of a write-only register, but an error does not occur. nothing changes even if data is written to a read-only register, and an error does not occur. an undefined value is read if an unused address is read; nothing changes even if data is written to this address. an error does not occur.
m pd17201a, 17207 25 4.5 register file (rf) the register file mainly consists of registers that set the conditions of the peripheral hardware. these registers can be controlled by dedicated instructions peek and poke, and the embedded macro instructions of as17k, setn, clrn, and initflg. 4.5.1 configuration of register file fig. 4-9 shows the configuration of the register file and how the register file is accessed by the peek and poke instructions. the control registers are controlled by using dedicated instructions peek and poke. since the control registers are assigned to addresses 00h-3fh regardless of the bank, the addresses 00h-3fh of the general-purpose data memory cannot be accessed when the peek or poke instruction is used. the addresses that can be accessed by the peek and poke instructions are the addresses 00h-3fh of the control registers and 40h-7fh of the general-purpose data memory. the register file consists of these addresses. the control registers are assigned to addresses 80h-bfh on the ie-17k to facilitate debugging. fig. 4-9 configuration of register file and accessing register file by peek and poke instructions bank0 column address data memory ld poke peek m030, wr rf73, wr wr, rf70 st wr, m032 wr 0 1 2 3 4 5 6 7 0 1 2 3 peek wr, rf11 poke rf33, wr r o w a d d r e s s system registers control registers register file 0 12 3 45678 9 abc de f
m pd17201a, 17207 26 4.5.2 control registers the control registers consists of a total of 64 nibbles (64 x 4 bits) of the addresses 00h-3fh of the register file. of these, however, only 20 nibbles are actually used. the remaining 44 nibbles are unused registers that are inhibited from being read or written. when the peek wr, rf instruction is executed, the contents of the register file addressed by rf are read to the window register. when the poke rf, wr instruction is executed, the contents of the window register are written to the register file addressed by rf. when using the 17k series assembler, the macro instructions listed below, which are embedded as flag type symbol manipulation instructions, can be used. the macro instructions allow the contents of the register file to be manipulated in bit units. for the configuration of the control register, refer to fig. 15-1 register file list. setn : sets flag to 1 clrn : sets flag to 0 sktn : skips if all flags are 1 skfn : skips if all flags are 0 notn : complements flag initflg : initializes flag 4.5.3 notes on using register files when using the register files, bear in mind the points described below. for details, refer to m pd172xx subseries users manual . (1) when manipulating control registers (read-only and unused registers) when manipulating the read-only (r) and unused control registers by using the assembler or in-circuit emulator, keep in mind the following points: ? when device operates nothing changes even if data is written to the read-only register. if the unused register is read, an undefined value is read; nothing is changed even if data is written to this register. ? using 17k series assembler an error occurs if an instruction is executed to write data to the read-only register. an error also occurs if an instruction is executed to read or write the unused address. ? when an in-circuit emulator (ie-17k or ie-17k-et) is used (when instruction is executed for patch processing) nothing changes even if data is written to the read-only register, and an error does not occur. an undefined value is read if the unused address is read; nothing changes even if data is written to this address. an error does not occur.
m pd17201a, 17207 27 (2) symbol definition of register file an error occurs if a register file address is directly specified as a numeral by the operand rf of the peek wr, rf or poke rf, wr instruction if the 17k series assembler is being used. therefore, the addresses of the register file must be defined in advance as symbols. to define the addresses of the control registers as symbols, define them as the addresses 80h-bfh of bank0. the portion of the register file overlapping the data memory (40h-7fh), however, can be defined as symbols as is.
m pd17201a, 17207 28 5. ports 5.1 port 0a this port is a 4-bit i/o port. the four bits of this port are assigned all inputs or all outputs. this assignment is performed by p0agio of the register file. transferring data from and to this port is performed via the p0a port register (address 70h of bank0). this port is set in the input mode at reset. this port can release the standby mode when the standby mode has been set and if all the bits of the port are not set at high level. this port is connected to the pull-up resistor regardless of whether the input or output mode is specified. 5.2 port 0b this port is a 4-bit i/o port. the four bits of this port are assigned all inputs or all outputs. this assignment is performed by p0bgio of the register file. transferring data from and to this port is performed via the p0b port register (address 71h of bank0). this port is set in the input mode at reset. this port can release the standby mode when the standby mode has been set and if all the bits of the port are not at low level. in the output mode, this port requires an external pull-up resistor because it works as an n-ch open-drain output. 5.3 port 0c this port is a 4-bit i/o port. the four bits of this port are assigned all inputs or all outputs. this assignment is performed by p0cgio of the register file. transferring data from and to this port is performed via the p0c port register (address 72h of bank0). this port is set in the input mode at reset. in the output mode, this port requires an external pull-up resistor because it works as an n-ch open-drain output. 5.4 port 0d this port works as a 4-bit i/o port, an led output, and an external signal output for the 8-bit timer. one of these functions is selected by nrzen and tmoe of the register file. (1) using the whole port as a 4-bit i/o port the pins of this port can be individually assigned input or output. this assignment is performed by p0dbio3 to p0dbio0 of the register file. transferring data from and to this port is performed via the p0d (address 73h of bank0). (2) using the p0d 0 pin as an led output the led output pin and the i/o port (p0d 0 ) pins are selected by nrzen. the led output pin outputs an nrz signal in synchronization with the rem output. (3) using the p0d 1 pin as an external signal output for the 8-bit timer the external signal output pin for the 8-bit timer and the i/o port (p0d 1 ) pins are selected by tmoe.
m pd17201a, 17207 29 5.5 port 1a this port works as a 3-bit general i/o port and as serial interface. the i/o port or serial interface is selected by sioen of the register file. (1) using the port 1a as a 3-bit i/o port the three bits of the port 1a can be assigned all inputs or all outputs. this assignment is performed by p1agio of the register file. transferring data from and to this port is performed via the p1a (address 70h of bank1). (2) using port 1a as serial interface serial interface or the i/o port (p1a 0 , p1a 1 , and p1a 2 ) is selected by sion. 5.6 int pin this pin inputs an external interrupt request signal. at the rising edge of the signal input to this pin, the irq flag (rf: address 3dh, bit 1) is set. the status of the pin can be read by using the int flag (rf: address 0fh, bit 0). when a high level is input to the int pin, the int flag is set to 1; when a low level is input, the int flag is reset to 0 (refer to fig. 12-1 int flag ). table 5-1 relations between port registers and pins bank add- port bit output read contents written contents at reset ress format input mode output mode input mode output mode b 3 p0a 3 70h port 0a b 2 p0a 2 cmos output latch b 1 p0a 1 push-pull b 0 p0a 0 b 3 p0b 3 71h port 0b b 2 p0b 2 n-ch pin status b 1 p0b 1 open-drain 0 b 0 p0b 0 b 3 p0c 3 72h port 0c b 2 p0c 2 n-ch pin status output latch b 1 p0c 1 open-drain b 0 p0c 0 input mode b 3 p0d 3 73h port 0d b 2 p0d 2 cmos output latch b 1 p0d 1 note1 push-pull b 0 p0d 0 note1 b 3 C 1 70h port 1a b 2 p1a 2 note2 cmos b 1 p1a 1 note2 push-pull b 0 p1a 0 note2 notes 1. when the nrzen and tmoe flags are set to 1, the output latch is accessed both when these port pins are read and when they are written, regardless of whether the input or output mode is set. 2. when the sioen flag is set to 1, these pins serve as serial interface pins. in this case, the statuses of the pins are read when the pins are read, regardless of the input or output mode. data written to these pins is invalid. input mode (w/pull-up resistor)
m pd17201a, 17207 30 5.7 port control register 5.7.1 switching between input and output of grouped i/o port a grouped i/o port is a port whose four bits are assigned all inputs or all outputs at a time. grouped i/o ports are p0a, p0b, p0c, p0d, and p1a. their selection of inputs or outputs is performed by the following i/o control register. when the bits of each port are assigned from inputs to outputs, its output latch is output to the port. fig. 5-1 i/o control register for grouped i/o ports p0agio 0 1 places port 0a in input mode places port 0a in output mode function p0bgio 0 1 places port 0b in input mode places port 0b in output mode function p0cgio 0 1 places port 0c in input mode places port 0c in output mode function p1agio 0 1 places port 1a in input mode places port 1a in output mode function bit 3 bit 2 bit 1 bit 0 p1agio p0cgio p0bgio p0agio r/w r/w r/w 0000 read/write default at reset r: read, w: write rf: address 37h r/w
m pd17201a, 17207 31 5.7.2 switching between input and output of bitwise i/o port a bitwise i/o port is a port whose four bits are individually assigned inputs or output. the m pd17207 supports only one bitwise i/o port: p0d. the bitwise input/output selection is performed by the following i/o control register. when the bits of this port are assigned from inputs to outputs, output latches of p0a, p0b, p0c, p0d, and p1a are output to the corresponding ports. fig. 5-2 i/o control register for bitwise i/o ports p0dbio0 0 1 places p0d 0 in input mode function p0dbio1 0 1 function p0dbio2 0 1 function p0dbio3 0 1 function bit 3 bit 2 bit 1 bit 0 p0dbio 3 p0dbio 2 p0dbio 1 p0dbio 0 r/w 0000 read/write default at reset r: read, w: write rf: address 27h places p0d 0 in output mode places p0d 1 in input mode places p0d 1 in output mode places p0d 2 in input mode places p0d 2 in output mode places p0d 3 in input mode places p0d 3 in output mode r/w r/w r/w
m pd17201a, 17207 32 5.7.3 switching among port, timer output, and led output the functions of port 0d (port, timer output, and led output) are selected by settings of the tmoe and nrzen bits of register file (tmoe for p0d 1 and nrzen for p0d 0 ). refer to fig. 5-3 . 5.7.4 switching between port and serial interface the functions of port 1a (port and serial interface) are selected by settings of the sioen bit of register file. refer to fig. 5-3 . the mode of serial interface is controlled by siots (bit 3 of address 22h), siohiz (bit 2 of address 22h), siock1 (bit 1 of address 22h), and siock0 (bit 0 of address 22h) of register file. fig. 5-3 input/output control register for selection of port, timer output, led output, and serial interface sioen 0 1 uses port 1a as i / o port uses port 1a as serial interface function tmoe 0 1 uses p0d 1 as i / o port uses p0d 1 external signel output for 8-bit timer's function nrzen 0 1 uses p0d 0 as i / o port uses p0d 0 as led output function bit 3 bit 2 bit 1 bit 0 0 nrzen tmoe sioen r r/w 0000 read/write default at reset r: read, w: write rf: address 23h r/w r/w
m pd17201a, 17207 33 6. clock generator circuit the m pd17207 contains two types of oscillator circuits: the main clock (x) and the subclock (xt) oscillator circuits. the clock oscillated by either of the circuits can be used as the system clock. figure 6-1 shows the configuration of the system clock control register. whether the main or subclock is used as the system clock is specified by the sysck flag (rf: address 02h, bit 1). by resetting the xen flag (rf: address 02h, bit 0), oscillation of the main clock can be stopped to reduce current dissipation. to use the subclock, be sure to connect a 0.1- m f capacitor to the v reg pin to stabilize the oscillation of the subclock. when the subclock is not used (which is specified by mask option), connect the xt in pin to gnd, and xt out pin to v reg pin. fig. 6-1 system clock control register specifies mask option initial value at reset remark main clock subclock sysck xen used (usex) used (usext) 1 1 value can be changed note not used (noxt) 1 1 fixed value (cannot be not used (nox) used (usext) 0 0 changed in software) note sysck cannot be changed to 1 and xen cannot be changed to 0. xen 0 1 function sysck 0 1 function bit 3 bit 2 bit 1 bit 0 0 0 sysck xen r/w 00 read/write default at reset r: read, w: write rf: address 02h refer to the table below . (by mask option) stops main clock oscillates main clock selects subclock as system clock selects main clock as system clock
m pd17201a, 17207 34 6.1 switching system clock the system clock can be switched between the main clock and subclock by using the sysck flag (rf: address 02h, bit 1) as shown in fig. 6-1. (1) switching from main clock to subclock the system clock can be changed from the main clock to subclock by resetting the sysck flag to 0. when noxt is set by mask option, however, the subclock cannot be selected (sysck and xen cannot be reset to 0). caution when turning on the power, make sure that a sufficient time elapses to stabilize the oscillation of the subclock (confirm that the irqwtm flag (rf: address 3ch, bit 2) is set by the program at a specific cycle). (2) switching from subclock to main clock the system clock can be changed from the subclock to the main clock by setting the sysck flag to 1. when nox is set by mask option, however, the main clock cannot be selected (sysck and xen cannot be set to 1). caution before setting the sysck flag, make sure that at least 10 ms elapses after the xen flag has been set to 1 so that the oscillation stabilizes. 6.2 main clock oscillation control function when the subclock is used as the system clock, oscillation of the main clock can be controlled by manipulating the xen flag (rf: address 02h, bit 0). if the system clock is changed from the subclock to main clock (by setting the sysck flag) after the main clock is started (by setting the xen flag), make sure that an oscillation stabilization time of about 10 ms elapses. caution do not manipulate the xen and sysck flags simultaneously (execute the poke instruction twice).
m pd17201a, 17207 35 7. 8-bit timer and remote controller carrier generator circuit the 8-bit timer is mainly used to generate the leader pulse of the remote controller signal, and to output codes. operations of timers are controlled by the get instruction, the put instruction, and registers on the register file. 7.1 configuration of the 8-bit timer (with modulo function) figure 7-1 shows the functional block diagram of the 8-bit timer. the 8-bit timer consists of an 8-bit counter (tmc), an 8-bit modulo register (tmm), a comparator which compares the contents of the timer with the contents of the modulo register, and a selector which selects a count clock of the 8-bit timer. starting/stopping of the 8-bit timer and resetting of the 8-bit counter are controlled by tmen (bit 3 of address 33h) and tmres (bit 2 of address 33h) of the register file. the count clock of the 8-bit timer is selected by tmck1 (bit 1 of address 33h) and tmck0 (bit 0 of address 33h) of the register file. the contents of the 8-bit counter are read via the data buffer (dbf) by the get instruction. the user cannot write any value in the 8-bit counter. the user can set a value in the modulo register by the put instruction via the data buffer (dbf). the user cannot read the contents of the modulo register. as the 8-bit counter (tmc) and the modulo register (tmm) use an identical address, the cpu accesses the 8-bit counter to read and the 8-bit modulo register to write. when the current count value of the counter and the value of the modulo register coincide with each other, the interrupt request flag (irqtm: address 3eh, bit 0) is set, reflecting the output of the pod 1 /tmout pin. tmout is initialized and outputs a high level when tmres is set. caution do not clear tmm to 0 (irqtm cannot be set.) 76543210 tmm tmc 8-bit counter 76543210 8-bit modulo register address peripheral register: 02h at reset 00h r/w r address peripheral register: 02h at reset ffh r/w w
m pd17201a, 17207 36 fig. 7-1 configuration of 8-bit timer and remote controller carrier generator circuit remarks 1. f sys (system clock frequency): f x or f xt 2. tmm, tmc, nrzltmm and nrzhtmm are peripheral register. data buffer rf: 33h tmen tmres tmck1 tmck0 8-bit modulo register tmm comparator 8-bit counter tmc tout f/f selector q r s f sys /32 f sys /64 f sys //256 f sys /2 irqtm p0d 1 / tmout pin 6-bit modulo register nrzltmm comparator 6-bit modulo register nrzhtmm comparator led rem nrzbf nrz rf: 11h rf: 12h 8-bit timer remote controller carrier generator circuit internal bus sw 6-bit counter 6-bit counter
m pd17201a, 17207 37 7.2 function of the 8-bit timer (with modulo function) fig. 7-2 8-bit timer control register note this bit is always set to 1 when the stop mode is released. tmck 1, tmck 0 0 0 count clock : f sys /32 (test time range : 8 s to 2.048 ms) remarks 1 1 tmres 0 1 read data is always 0. resets 8-bit timer and irqtm. bit 3 bit 2 bit 1 bit 0 tmen tmres tmck1 tmck0 r/w w r/w 1 note 000 read/write default at reset r: read, w: write rf: address 33h tmen 0 1 stops 8-bit timer. starts 8-bit timer. (falling edge) 0 1 0 1 count clock : f sys /64 (test time range : 16 s to 4.096 ms) count clock : f sys /256 (test time range : 64 s to 16.384 ms) output of the remote controller carrier generator bit 0 bit 1 ( ) : value at f sys (system clock) = 4 mhz r/w
m pd17201a, 17207 38 7.3 remote controller carrier generator the m pd17207 is equipped with a circuit to generate carriers for the remote controller. this circuit consists of a 6-bit counter, a modulo register (nrzhtmm) to determine an nrz high-level period, a modulo register (nrzltmm) to determine an nrz low-level period, and a comparator. a carrier duty factor and a carrier frequency are determined by the contents of these modulo registers. the values of the high- and low-level periods are set in the corresponding modulo registers via the data buffers (dbf). a clock signal input to the 6-bit counter is obtained by dividing the frequency of the system clock signal by two (e.g, 2 mhz with a system clock of 4 mhzf x or 16.384 khz with a system clock of f xt = 32.768 khz). modulo registers nrzhtmm and nrzltmm are respectively resident on peripheral addresses 04h and 03h. these registers can be written by the put instruction and read by the get instruction 7.3.1 remote controller signal output control the output of the rem pin which outputs carriers is controlled by nrz (bit 0, address 12h of the register file), nrzbf (bit 0, address 11h of the register file), and an 8-bit timer. while nrz is 1, the rem pin outputs a carrier signal generated by the remote controller carrier generator. while nrz is 0, the output of the rem pin is low. the contents of the nrzbf are automatically set in the nrz flag by an interrupt signal generated by the 8-bit timer. when data is set in the nrzbf flag in advance, the status of the output of the rem pin varies in synchronization with the counting operation of the 8-bit timer. the content of the nrz flag is output to the led pin. namely, the led pin outputs a high-level signal when nrz is 1 and a low-level signal when nrz is 0. if the 8-bit timer generates an interrupt signal when the output of the rem pin is high, that is, when nrz is 1 and a carrier signal is high, the output of the rem pin does not match the contents of nrz until the carrier signal goes low. this operation is required to hold the pulse width of high carrier pulses constant. (see fig. 7-3.) when nrz is 0, the carrier generation circuit stops. in a system using the output of the remote controller carrier generator as a clock signal for the 8-bit timer, clock pulses are continuously supplied even after nrz has become 0. fig. 7-3 remote controller carrier output note this is the value when (tmck1, tmck0) (1,1). the value when (tmck1, tmck0) = (1, 1) differs depending on the manipulation of nrz. if nrz is set to 1 by an instruction, the width of the first high-level pulse may be narrowed. if nrz is set by means of transfer from nrzbf, the delay in the above chart is equivalent to the low-level pulse width of the carrier clock. led(nrz) rem delay note the rem pin does not go low before the carrier signal goes low even when nrz is 0 .
m pd17201a, 17207 39 fig. 7-4 register to control output signals of the remote controller bit 3 bit 2 bit 1 bit 0 0 0 0 nrz read / write r r r/w default at reset 0 0 0 r: read, w: write rf: address 12h r 0 nrz 0 1 outputs low-level signal to rem pin and low-level signal to led pin. bit 3 bit 2 bit 1 bit 0 0 0 0 nrzbf read / write r r r/w default at reset 0 0 0 r: read, w: write rf: address 11h r 0 nrzbf 0 1 nrz buffer bit. contents of this bit are transferred to nrz by interrupt signal generated by 8-bit timer. outputs carrier signal to rem pin and high-level signal to led pin.
m pd17201a, 17207 40 fig. 7-5 input/output control register for port/timer output, led output, and serial interface 7.3.2 setting a carrier frequency and a duty factor frequency division ratio necessary for obtaining carrier frequency f c can be calculated by the following expression where the frequency of main clock (x) is f x . = f x /(2 x f c ). set the following values to the modulo register to divide into duty factors m: n. high-level period setting value (nrzhtmm) = x m/(m + n) C 1 low-level period setting value (nrzltmm) = x n/(m + n) C 1 example: where f x = 4 mhz, f c = 38 khz, and duty factor = 1/3 (m:n = 1:2) = 4 mhz/(2 x 38 khz) = 52.6 therefore, the values of the modulo registers are as follows: high-level period (nrzhtmm) = 17 (11h) low-level period (nrzltmm) = 34 (22h) calculating the carrier frequency with these values, f c = f x /(2 x ) = 4 mhz/(2 x 53) = 37.74 khz (where = (17 + 1) + (34 + 1) = 53) . . . . . . . . rf: address 23h bit 3 bit 2 bit 1 bit 0 0 n r z e n t m o e s i o e n r r/w r/w r/w 00 00 read/write initial value at reset tmoe read = r, write = w 0 function uses p0d 1 as i/o port pin 1 uses p0d 1 as external signal output pin of 8-bit timer 0 function 1 nrzen uses p0d 0 as i/o port pin uses p0d 0 as led output pin
m pd17201a, 17207 41 table 7-1 example of carrier frequency (f x = f sys = 4 mhz) set value t h ( m s) t l ( m s) 1/f c ( m s) f c (khz) duty nrzhtmm nrzltmm 00h 00h 0.5 0.5 1.0 1000 1/2 01h 02h 1.0 1.5 2.5 400 2/5 04h 04h 2.5 2.5 5.0 200 1/2 09h 09h 5.0 5.0 10.0 100 1/2 0fh 10h 8.0 8.5 16.5 60.6 1/2 0fh 21h 8.0 17.0 25.0 40.0 1/3 11h 21h 9.0 17.0 26.0 38.5 1/3 11h 22h 9.0 17.5 26.5 37.7 1/3 19h 35h 13.0 27.0 40.0 25.0 1/3 3fh 3fh 32.0 32.0 64.0 15.6 1/2 rem (f ) c t h t l 1/f c
m pd17201a, 17207 42 remarks 1. the int and reset pins are multiplexed with test pins (refer to 3.4 notes on using reset and int pins ). 2. in this figure, the reset pin is connected to a pull-up resistor by mask option. 7.3.3 countermeasures against noise during transmission (carrier output) when a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 a may flow through the infrared led. since two batteries are usually used as the power source of the transmitter, several w of equivalent resistance (r) exists in the power source as shown in fig. 7-6. this resistance increases from 10 to 20 w if the supply voltage drops to 2 v. while the carrier is output from the rem pin (while the infrared led lights), therefore, a high-frequency noise may be generated on the power lines due to the voltage fluctuation that may take place especially during switching. to minimize the influence on the microcontroller of this high-frequency noise, take the following measures: 1 separate the power lines of the microcontroller from the power lines of the infrared led with the terminals of the batteries at the center. use thick power lines and keep the wiring short. 2 locate the oscillator as close as possible to the microcontroller and shield it with gnd lines (as indicated by the portion inside the dotted line in the figure below). 3 locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller. also, use a capacitor to eliminate high-frequency noise. 4 to prevent data from changing, do not execute an interrupt that requires read/write processing and stack, such as key scan interrupt, and the call/ret instruction, while the carrier is output. 5 to improve the reliability in case of program hang-up, use the watchdog timer (connect the wdout and reset pins). fig. 7-6 example of countermeasures against noise 0.5 to 1 a infrared led rem v dd reset wdout microcontroller + _ r batteries v ss
m pd17201a, 17207 43 8. watch timer/watchdog timer the watch timer is used to generate a watch interrupt signal and a signal to reset the watchdog timer. 8.1 configuration of watch timer/watchdog timer figure 8-1 shows the functional block diagram of the watch timer/watchdog timer. as shown in fig. 8-1, the watch timer consists of two selectors, a and b, and a frequency divider. selector a selects the divided output (f x /2 7 ) of the 32.768-khz subclock oscillator (xt) output or of the main clock oscillator (x) output as the source clock by using mask option. selector b selects a frequency to be used as an interrupt signal. the divider creates a frequency of the source clock. resetting the watch timer and the operation of selector b is controlled by wtmres (address 03h, bit 1) and wtmmd (address 03h, bit 2) of the register file. the watchdog timer is reset by wdtres (address 03h, bit 3) of the register file. if the subclock (f xt ) is the source clock, the watch timer count cannot be stopped. therefore, the subclock does not stop but continues to oscillate even when the cpu is in the stop mode. if the divided output of the main clock (f x /2 7 ) is the source clock (when the subclock is not used), the watch timer stops when the cpu is set in the stop mode. fig. 8-1 configuration of watch timer/watchdog timer remark ( ) indicates the value when the subclock is used. note the source clock of the watch timer/watchdog timer is fixed as follows by mask option: 1 when subclock is selected by mask option the source clock is fixed to the subclock. 2 when subclock is not selected by mask option the source clock is fixed to f x /2 7 w t m m d w d t r e s w t m r e s lcd controller / driver selector b selector a note sub clock f xt (32.768 khz) f w (32.768 khz) main clock f x 1/2 11 division 1/2 division 1/2 division frequency divider f w /2 13 (4 hz) f w /2 11 (16 hz) f w /2 14 (2 hz) wdout irqwtm rf bit 2 address 3fh 1/2 division 1/2 7 division : f w /2 13 (4 hz)
m pd17201a, 17207 44 8.2 function of watch timer/watchdog timer fig. 8-2 watch timer/watchdog timer control register wtmres 0 1 read data is always 0 . resets watch timer when 1 is written. bit 3 bit 2 bit 1 bit 0 wdtres wtmmd wtmres 0 w w r/w r 0000 read/write default at reset r: read, w: write rf: address 03h wtmmd turns on ( 1 ) irqwtm for each f w /2 13 (4 hz). function 0 1 read data is always 0 . resets watchdog timer when 1 is written. wdtres 0 1 turns on ( 1 ) irqwtm for each f w /2 11 (16 hz). remark ( ) indicates the value when the subclock is used.
m pd17201a, 17207 45 8.3 watchdog timer operation timing unless the watchdog timer is reset in a fixed time, the wdout pin outputs a low level. by connecting the wdout pin to the reset pin, a program hang-up can be detected by the watchdog timer. to reset the watchdog timer, set wdtres (wdtres = 1). to disable hang-up detection by the watchdog timer when the subclock is used, program so that wdtres is set at intervals of approximately 340 ms or less. cautions 1. the watchdog timer cannot be reset in the shaded range in fig. 8-3. therefore, set the watchdog timer before both the f w /2 13 and f w /2 14 signals go high. 2. for further information on the wdout pin, also refer to 14. reset. fig. 8-3 watchdog timer operation timing remark figures in the parentheses indicate the value when using the subclock. f w /2 11 (16hz) f w /2 12 (8hz) f w /2 13 (4hz) f w /2 14 (2hz) intwtm (at 4hz) intwtm (at 16hz) wdout watchdog timer reset signal wdtres setting wdtres is invalid during this period wdout output goes low if wdtres is not set
m pd17201a, 17207 46 9. a/d converter the m pd17207 has an 8-bit successive approximation a/d converter. this a/d converter can be used in the following two modes. mode description a/d conversion mode converts analog voltage input to one pin into digital signal compare mode compares analog voltages input to two pins 9.1 configuration of a/d converter the 8-bit a/d converter consists of a selector that selects an input pin, analog switch, control circuit, 8-bit resistor string d/a converter, and comparator. fig. 9-1 block diagram of a/d converter register file adcch1 adcch0 adcen vrefen adc 0 adc 1 adc 2 adc 3 selector control circuit comparator register file + C adccmp analog switch 8-bit d/a converter adcr peripheral hardware power supply to a/d converter block v adc
m pd17201a, 17207 47 9.2 function of a/d converter 9.2.1 function in a/d conversion mode in the a/d conversion mode, the a/d converter compares an analog voltage input to one of the pins adc3 through ad0 with an internal reference voltage and outputs the result to adccmp on the register file. the pin from which an analog voltage is to be input is selected by the operation mode register (refer to figure 9-2 ). two or more pins cannot be selected for a/d conversion at the same time. the internal reference voltage is created by the 8-bit d/a converter based on the data set by the internal reference voltage setting register (adcr). the 8-bit d/a converter can create 256 values of the internal reference voltage. by selecting an internal reference voltage and executing successive approximation in software, the input analog voltage can be converted into a digital value. operation mode register selected function vrefen adcen adcch1 adcch0 input pin 1100adc 0 compares analog voltage input to adc 0 pin with internal reference voltage 0 1 adc 1 compares analog voltage input to adc 1 pin with internal reference voltage 1 0 adc 2 compares analog voltage input to adc 2 pin with internal reference voltage 1 1 adc 3 compares analog voltage input to adc 3 pin with internal reference voltage 9.2.2 function in compare mode in the compare mode, analog voltages input two of the pins adc 3 through adc 0 are compared with each other and the result is output to adccmp in the register file. the two pins from which analog voltages are to be input are selected by the operation mode register (refer to figure 9-2 ). two pairs of pins can be selected: pins adc 2 and adc 0 , pins or adc 3 and adc 1 . both pairs of pins cannot be selected at the same time. operation mode register selected function vrefen adcen adcch1 adcch0 input pin 0010adc 2 compares analog voltages input to adc 2 and adc 0 pins adc 0 1 1 adc 3 compares analog voltages input to adc 3 and adc 1 pins adc 1
m pd17201a, 17207 48 9.3 control registers of a/d converter 9.3.1 operation mode register the operation mode register selects the operation mode and analog input pin(s) of the a/d converter by using the flags in the register file as illustrated below. fig. 9-2 operation mode register rf: address 21h bit 3 bit 2 bit 1 bit 0 v r e f e n a d c e n a d c c h 1 a d c c h 0 read/write initial value at reset r/w 00 00 vrefen adcen adcch1 adcch0 operation mode 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 don care read = r, write = w selected analog input pin +side of internal comparator eside of internal comparator adc 2 pin adc 3 pin adc 0 pin adc 1 pin adc 2 pin adc 3 pin none undefined adc 0 pin adc 1 pin (internal reference voltage) (internal reference voltage) (internal reference voltage) (internal reference voltage) others compare compare a/d conversion a/d conversion a/d conversion a/d conversion operation stops setting prohibited caution set the operation stop mode to reduce the current consumption when the a/d converter is not used.
m pd17201a, 17207 49 9.3.2 internal reference voltage setting register (adcr) the internal reference voltage setting register (adcr) is an 8-bit register that sets the reference voltage of the converter. this register is allocated to the peripheral hardware. data is written to the adcr via data buffer (dbf). the 8-bit data set to dbf0 and dbf1 is written to the adcr by using the put adcr, dbf instruction. 9.3.3 compare result register the result of comparison by the converter is stored to the adccmp flag in the register file. fig. 9-3 compare result register rf: address 20h bit 3 bit 2 bit 1 bit 0 000 a d c c m p read/write initial value at reset 0 0 0 0 r adccmp read = r [in compare mode] adccmp result of comparison 0 1 adc 2 voltage < adc 0 voltage adc 3 voltage < adc 1 voltage adc 2 voltage adc 0 voltage adc 3 voltage adc 1 voltage [in a/d conversion mode] adccmp result of comparison 0 1 adc n voltage < internal reference voltage adc n voltage internal reference voltage (n = 0 to 3)
m pd17201a, 17207 50 9.4 operation in a/d conversion mode the timing necessary for a/d conversion differs depending on whether the main clock or subclock is selected as the system clock. (1) when main clock is selected as system clock the following wait times must be set in software in the a/d conversion mode. wait time <1>: time of transition from operation stop mode to a/d conversion mode (8 instruction cycles) wait time <2>: wait time until value can be set to adcr (3 instruction cycles) wait time <3>: wait time until compare result register can be read (4 instruction cycles) sets a/d conversion mode (vrefen, adcen, adcch1, adcch0) wait time < 1 > + wait time < 2 > (11 instruction cycles) sets adcr (80h) reads adccmp (set + compare) wait time < 3 > (4 instruction cycles) wait time < 2 > (3 instruction cycles) wait time < 3 > (4 instruction cycles) wait time < 2 > (3 instruction cycles) (set + compare) sets adcr (40h or 0c0h) reads adccmp an example of a program for a/d conversion when the main clock is selected is shown below.
m pd17201a, 17207 51 cmpval dat 80h ; reference voltage =v adc cmpval/256 adcnv: bank0 initflg vrefen,adcen,not adcch1,not adcch0 ; starts sampling of input to adc 0 mov dbf0, #cmpval and 0fh mov dbf1, #cmpval shr 4 and 0fh rept 9 nop endr put adcr,dbf ; holds input and starts comparison nop nop nop nop peek wr,.mf.adccmp shr 4 and 0fffh ; reads result of comparison (starts sampling) mov dbf0, #cmpval and 0fh mov dbf1, #cmpval shr 4 and 0fh nop put adcr, dbf ; holds input and starts comparison nop nop nop nop peek wr,.mf.adccmp shr 4 and 0fffh ; reads result of comparison (starts sampling) (2) when subclock is being selected as system clock unlike when the main clock is selected, the wait times do not need to be set in software when the subclock is selected. setting the a/d conversion mode, adcr, and reading adccmp are completed in one instruction cycle, respectively. an example of a program for a/d conversion when the subclock is selected is shown below. cmpval dat 80h ; reference voltage = v adc cmpval/256 adcnv: bank0 initflg vrefen,adcen,not adcch1,not adcch0 ; starts sampling a voltage input to the adc 0 pin. mov dbf0,#cmpval and 0fh mov dbf1,#cmpval shr 4 and 0fh put adcr,dbf ; holds the input and starts comparison peek wr,.mf.adccmp shr 4 and 0fffh ; reads the result of comparison (and starts sampling). waits for at least 11 instruction cycles until adcr is set waits for at least 4 instruction cycles until adccmp is checked waits for at least 3 instruction cycles until adcr is set waits for at least 4 instruction cycles until adccmp is checked
m pd17201a, 17207 52 9.5 operation in compare mode in the compare mode, the result of comparison stored to adccmp is read and then the next comparison is immediately performed. therefore, comparison is executed successively and the adccmp flag is rewritten accordingly. the timing necessary for compare mode differs depending on whether the main clock or subclock is selected as the system clock. (1) when main clock is selected as system clock the following wait times must be set in software in the compare mode. wait time <1>: time of transition from operation stop mode to compare mode (10 instruction cycles) wait time <2>: wait time until compare result register can be read (first time only) (3 instruction cycles) wait time <3>: wait time until compare result register can be read (second time and onward) (7 instruction cycles) sets compare mode or changes pin (vrefen, adcen, adcch1, adcch0) (set + compare) wait time < 1 > + wait time < 2 > (13 instruction cycles) (compare) wait time < 3 > (7 instruction cycles) (compare) wait time < 3 > (7 instruction cycles) (compare) wait time < 3 > (7 instruction cycles) reads adccmp reads adccmp reads adccmp an example of a program in the compare mode when the main clock is selected is shown below. compare: initflg not vrefen,not adcen,adcch1,adcch0 ; starts comparing voltages of adc 3 and adc 1 rept 13 nop endr peek wr,.mf.adccmp shr 4 and 0fffh ; reads result of comparison rept 7 nop endr peek wr,.mf.adccmp shr 4 and 0fffh ; reads result of comparison waits for duration of 13 instruction cycles or more until comparison ends waits for duration of 7 instruction cycles or more until comparison ends
m pd17201a, 17207 53 (2) when subclock is selected as system clock the following wait times must be set in software during compare operation. wait time: time of transition from operation stop mode to compare mode (2 instruction cycles) sets compare mode (vrefen, adcen, adcch1, adcch0) (set + compare) wait time (2 instruction cycles) reads adccmp (compare) wait time: not necessary (compare) wait time: not necessary reads adccmp an example of a program in the compare mode when the subclock is selected is shown below. compare: initflg not vrefen,not adcen,adcch1,adcch0 ; starts comparing voltages on adc 3 and adc 1 nop waits for duration of 2 instruction cycles nop or more until comparison ends peek wr,.mf.adccmp shr 4 and 0fffh ; reads result of comparison peek wr,.mf.adccmp shr 4 and 0fffh ; reads result of comparison
m pd17201a, 17207 54 10. serial interface serial interface consists of an 8-bit shift register, a 4-bit shift mode register, and a 3-bit counter, and transmits data in series to and from the bus. 10.1 serial interface function 10.1.1 8-bit data transfer in synchronization with clocks (simultaneous transmission and reception) input and output of serial data on serial interface is controlled by the serial clock (sck) signal. at the falling edge of the sck signal, the most significant bit of the shift register is output from the so pin (pin 59; also used as p1a 1 ). at the rising edge of the sck signal, the contents of the shift register are shifted left by one bit and, at the same time, data input via the si pin (pin 60; also used as p1a 2 ) is set in the least significant bit of the shift register. the 3-bit counter counts serial clock pulses. each time the counter counts eight clock pulses (each time serial data of 8 bits is transferred), the irqsio flag (bit 3, address 3bh) of the register file is turned on (1) to make an interrupt request. 10.1.2 8-bit data reception in synchronism with clocks (high-impedance so output) this operation is basically the same as the above operation except that the si pin (pin 59; also used as p1a 1 ) goes into a high-impedance state and does not output serial data. therefore, the so pin can be used as a port (p1a 1 ). 10.2 serial interface operation 10.2.1 serial interface operation modes p1a 2 /si (pin 60), p1a 1 /so (pin 59), and p1a 0 /sck (pin 58) are placed in serial interface mode when the sioen flag (bit 0, address 23h) of the register file is turned on (1). these pins can be used as port pins when the sioen flag is off (0). as this operation mode disables transfer of serial data, the shift register can be used as an 8-bit registe r. 10.2.2 serial operation mode the serial operation mode is determined by the status of the siohiz flag (bit 2, address 22h) of the register file. when this flag is off (0), a clock-synchronous 8-bit transmission/reception mode is set. when this flag is on (1), a clock-synchronous 8-bit reception mode is set. figure 10-1 shows shift timing waveforms. the only difference between these two modes is whether the so pin (pin 59; also used as p1a 1 ) goes into a high-impedance state. in transmission of serial data, data to be transmitted is set in the shift register siosfr (peripheral address 01h) via the data buffer (dbf) by an put instruction, and the siots flag (bit3, address 22h) of the register file is turned on (1). thus serial data trasfer starts. when 8 bits of data are transferred, the siots flag is automatically turned off (0) and the irqsio flag (bit 3, address 3bh) of the register file is turned on (1) to generate an interrupt. if generation of an interrupt is disabled, the end of transfer can be indicated by the siots and irqsio flags. reception of serial data is basically the same as the transmission of serial data except that data is output from the so pin. the m pd17207 supports four kinds of clock signals (three internal clocks and one external clock) to be selected as the serial clock source. these clock signals are selected by siock1 (bit 1, address 22h) and siock0 (bit 0, address 22h) of the register file. if one of the three internal clock signals is selected as the serial clock source, it is supplied to serial interface when the siots flag turns on (1). the clock controls input/output of serial data and is output from the sck pin (pin 58; also used as p1a0). when eight clock pulses are supplied to the serial interface, the siots flag is automatically turned off (0) and the supply of clock pulses to the serial interface is stopped. then, the sck pin is held high. at this time, the irqsio flag (bit 3, address 3bh) of the register file is turned on (1).
m pd17201a, 17207 55 if the external clock is selected, the clock pulses supplied from the sck pin are supplied to serial interface when the siots flag is turned on (1). similarly, when eight clock pulses are supplied to the serial interface, the siots flag is automatically turned off (0) and the supply of clock pulses to the serial interface is stopped. at this time, the irqsio flag (bit 3, address 3bh) of the register file is turned on (1). the irqsio flag is automatically reset to 0 when the siots flag is turned on (1). to forcibly stop transfer of serial data, turn on the siots flag manually. note, however, that data transfer cannot be resumed from the point at which the transfer has been forcibly stopped. fig. 10-1 shift timing waveforms sck pin si pin so pin (siohiz=0) so pin (siohiz=1) irqsio 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 high-impedance turns on siots (1). turns off siots (0). (end of transfer) remark di : serial data input do : serial data output
m pd17201a, 17207 56 fig. 10-2 input/output control register for selection of port, timer output, led output, and serial interface function 0 1 uses port 1a as i / o port. uses port 1a as serial interface. bit 3 bit 2 bit 1 bit 0 0 r r/w 00 00 read/write default at reset rf: address 23h nrzen tmoe sioen sioen r: read, w: write r/w r/w
m pd17201a, 17207 57 fig. 10-3 serial interface control register selects serial clock 0 0 external clock so pin status 0 1 serial data output high-impedance status function 0 1 inhibits contents of shift register from being shifted. pin status can be read by instruction input from port. shifts contents of shift register by serial clock pulses. pin status can be read by instrucrtion input from port. bit 3 bit 2 bit 1 bit 0 siots 00 00 read/write default at reset rf: address 22h siohiz siock1 siock0 r/w siock1, siock0 siohiz siots [read] r: read, w: write 0 1 1 1 0 1 siock1, siock0 f sys /16 (f sys : system clock. f x or f xt ) f sys /128 f sys /1024 function 0 1 forcibly stops transfer of serial data. data transfer cannot be resumed from where it has been stopped. 3-bit counter is cleared. can be set by put instruction only. transfer of serial data starts. resets irqsio flag (to 0 ). this bit is automatically reset to 0 after transfer of data ends. [write] caution be sure to select a serial clock signal before starting transfer of serial data. never set them at the same time. remark at the end of transfer of 8-bit serial data, the irqsio flag (bit 3, address 3bh of the register file) is turned on (1) and an interrupt request occurs.
m pd17201a, 17207 58 11. lcd controller/driver 11.1 configuration of lcd controller/driver the m pd17207 is equipped with an lcd controller which generates segment and common signals according to the data set to the lcd register and a segment/common driver which can directly drive the lcd panel. figure 11-1 shows the functional block diagram of the lcd controller/driver. fig. 11-1 block diagram of lcd controller/driver 0 lcdd0 (40 h) lcdd1 (41 h) lcdd33 (61 h) lcdd34 (62 h) lcdd35 (63 h) l c d e n l c d c k 2 l c d c k 1 l c d c k 0 l c d m d 3 l c d m d 2 l c d m d 1 l c d m d 0 lcd 0 lcd 1 lcd 33 lcd 34 /com 3 lcd 35 /com 2 com 1 com 0 v lcd0 v lcd1 v lcd2 capl caph timing controller lcd register multiplexer data selector segment/common driver voltage booster circuit for lcd driver 12 3 0 12 3 0 12 3 0 12 3 0 12 3 0 12 3 0 12 3 0 12 3 0 12 3 0 12 3
m pd17201a, 17207 59 11.2 functions of lcd controller/driver the lcd controller/driver of the m pd17207 features the following: (1) automatically reads the lcd register and generates segment signals and common signals. (2) three display modes available: ? display mode 1: 1/2-duty, 1/3-bias ? display mode 2: 1/3-duty, 1/3-bias ? display mode 3: 1/4-duty, 1/3-bias (3) four frame frequencies available in each display mode. (4) since a voltage booster circuit for lcd driver is used, constant output voltage not affected by the fluctuation in the supply voltage. (5) the lcd register which is not used for display can be used as ordinary data memory. table 11-1 shows the maximum number of pixels available in each display mode. table 11-1 maximum number of pixels displayed mode duty common signal maximum number of pixels 1 1/2 com 0 , com 1 72 (36 segment signals by 2 common signals) 2 1/3 com 0 , com 1 , com 2 105 (35 segment signals by 3 common signals) 3 1/4 com 0 , com 1 , com 2 , com 3 136 (34 segment signals by 4 common signals) 11.3 display mode register the display mode register selects a display mode of the lcd controller/driver, a frame frequency, and lcd on/ off status. the display mode register consists of lcdmd0 to lcdmd3 (address 32h of register file) for selection of a display mode, lcden (bit 3, address 31h of the register file) for selection of the lcd on/off status, and lcdck0 to lcdck2 (bit 2 to bit 0, address 31h of the register file) for selection of a frame frequency.
m pd17201a, 17207 60 fig. 11-2 display mode register bit 3 bit 2 bit 1 bit 0 lcdmd3 lcdmd2 lcdmd1 lcdmd0 r r r/w r/w 0001 read/write default at reset rf: 32h read = r, write = w lcdmd3 lcdmd2 lcdmd1 lcdmd0 stops the lcd voltage booster circuit. note display mode 1 (1/2 duty) display mode 2 (1/3 duty) display mode 3 (1/4 duty) lcdmd0 _ lcdmd3 others display mode inhibited note all segment and common signals are at a preset voltage (v lcd0 ) 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0
m pd17201a, 17207 61 fig. 11-3 lcd controller/driver control register bit 3 bit 2 bit 1 bit 0 r r/w r/w 0000 read/write default at reset rf: 31h r/w 0 0 0 0 0 0 1 1 0 1 0 1 f w /(2 2 6 ) [256 hz] f w /(2 2 5 ) [512hz] [64 hz] [128 hz] f w /(3 2 6 ) [170 hz] [341.3 hz] [42.6 hz] [85.3 hz] f w /(4 2 6 ) [128 hz] [256 hz] [32 hz] [64 hz] lcdck2 lcdck1 lcdck0 lcdck0 _ lcdck2 mode 1 1/2 duty mode 2 1/3 duty mode 3 1/4 duty frame frequency others inhibited 1. f w = f xt or f x /2 7 2. [ ] : frequency for f w = 32.768 khz lcden 0 1 turns off the lcd display. (all segment signals are on unselected) turns on lcd display. function lcden remark lcden lcdck2 lcdck1 lcdck0 read = r, write = w f w /(3 2 5 ) f w /(4 2 5 ) f w /(2 2 8 ) f w /(3 2 8 ) f w /(4 2 8 ) f w /(2 2 7 ) f w /(3 2 7 ) f w /(4 2 7 )
m pd17201a, 17207 62 cautions 1. the lcd clock is supplied from the watch timer; therefore, the lcd flickers if the watch timer is reset during display. do not reset the watch timer during display. 2. if the main clock and subclock are used, the source clock of the lcd is the subclock. when the power is switched on, therefore, the lcd may flicker until the oscillation of the subclock stabilizes. make sure that a sufficiently long time elapses until the oscillation stabilizes before turning on the lcd (it is recommended that all-light mode be used immediately after power application). 3. the lcd display voltages (v lcd0 , v lcd1 , and v lcd2 ) become undefined momentarily on turning on/off power, reset, and setting or clearing the stop mode. as a result, the lcd display may be turned on (blurring of the lcd). this symptom is conspicuous when only the main clock is used or if the capacitance at the lcd display side is too high. to prevent this, take the following measures. ? provide wait time of 1 frame cycle or longer until the voltage booster circuit is stopped by the display mode register after the lcd display has been turned off. ? provide wait time of around 2 ms after the voltage booster circuit has been stopped until the stop instruction is executed.
m pd17201a, 17207 63 11.4 lcd register the lcd register is resident on addresses 40h to 63h (lcdd0 to lcdd35) of bank 0. the lcd controller/driver reads the lcd register independently of the operation of the cpu. the lcd controller controls segment signals according to the data of the lcd register. the data memory area which is not used for lcd display can be used as ordinary data memory. figure 11-4 shows the assignment of segment outputs to bits of the lcd register. fig. 11-4 assignment of common signals and segment signals to lcd register b 3 b 2 b 1 b 0 lcdd 0 (40 h) lcdd 1 (41 h) lcdd 2 (42 h) lcdd 33 (61 h) lcdd 34 (62 h) lcdd 35 (63 h) lcd 0 lcd 1 lcd 2 lcd 33 lcd 34 /com 3 lcd 34 /com 3 com 3 com 2 com 1 com 0 address
m pd17201a, 17207 64 fig. 11-5 wiring example of secondary time sharing lcd panel lcdd 0 (40 h) lcdd 1 (41 h) lcdd 2 (42 h) lcdd 3 (43 h) lcdd 4 (44 h) lcdd 5 (45 h) lcdd 6 (46 h) lcdd 7 (47 h) lcdd 8 (48 h) lcdd 9 (49 h) lcdd 10 (4 ah) lcdd 11 (4 bh) lcdd 12 (4 ch) lcdd 13 (4 dh) lcdd 14 (4 eh) lcdd 15 (4 fh) lcdd 16 (50 h) lcdd 17 (51 h) lcdd 18 (52 h) lcdd 19 (53 h) lcdd 20 (54 h) lcdd 21 (55 h) lcdd 22 (56 h) lcdd 23 (57 h) lcdd 24 (58 h) lcdd 25 (59 h) lcdd 26 (5 ah) lcdd 27 (5 bh) lcdd 28 (5 ch) lcdd 29 (5 dh) lcdd 30 (5 eh) lcdd 31 (5 fh) lcdd 32 (60 h) lcdd 33 (61 h) lcdd 34 (62 h) lcdd 35 (63 h) lcd0 lcd1 lcd2 lcd3 lcd4 lcd5 lcd6 lcd7 lcd8 lcd9 lcd10 lcd11 lcd12 lcd13 lcd14 lcd15 lcd16 lcd17 lcd18 lcd19 lcd20 lcd21 lcd22 lcd23 lcd24 lcd25 lcd26 lcd27 lcd28 lcd29 lcd30 lcd31 lcdd32 lcdd33 lcdd34 lcdd35 1 0 x x 1 1 x x 1 1 x x 1 1 x x 1 0 x x 1 0 x x 1 1 x x 0 0 x x 1 1 x x 0 1 x x 1 1 x x 1 1 x x 1 0 x x 0 1 x x 1 1 x x 0 1 x x 1 0 x x 1 1 x x 1 0 x x 0 0 x x 1 0 x x 1 1 x x 0 1 x x 0 1 x x 0 0 x x 1 1 x x 0 1 x x 1 1 x x 1 0 x x 1 0 x x 0 0 x x 0 0 x x 1 0 x x 1 0 x x 0 0 x x 0 0 x x com0 com1 bit0 bit1 bit2 bit3 strobe timing lcd panel x: any value because of secondary time sharing display.
m pd17201a, 17207 65 fig. 11-6 wiring example of tertiary time sharing lcd panel lcdd 0 (40 h) lcdd 1 (41 h) lcdd 2 (42 h) lcdd 3 (43 h) lcdd 4 (44 h) lcdd 5 (45 h) lcdd 6 (46 h) lcdd 7 (47 h) lcdd 8 (48 h) lcdd 9 (49 h) lcdd 10 (4 ah) lcdd 11 (4 bh) lcdd 12 (4 ch) lcdd 13 (4 dh) lcdd 14 (4 eh) lcdd 15 (4 fh) lcdd 16 (50 h) lcdd 17 (51 h) lcdd 18 (52 h) lcdd 19 (53 h) lcdd 20 (54 h) lcdd 21 (55 h) lcdd 22 (56 h) lcdd 23 (57 h) lcdd 24 (58 h) lcdd 25 (59 h) lcdd 26 (5 ah) lcdd 27 (5 bh) lcdd 28 (5 ch) lcdd 29 (5 dh) lcdd 30 (5 eh) lcdd 31 (5 fh) lcdd 32 (60 h) lcdd 33 (61 h) lcdd 34 (62 h) lcd0 lcd1 lcd2 lcd3 lcd4 lcd5 lcd6 lcd7 lcd8 lcd9 lcd10 lcd11 lcd12 lcd13 lcd14 lcd15 lcd16 lcd17 lcd18 lcd19 lcd20 lcd21 lcd22 lcd23 lcd24 lcd25 lcd26 lcd27 lcd28 lcd29 lcd30 lcd31 lcd32 lcd33 lcd34 com0 bit0 bit1 bit2 bit3 strobe timing 1 1 0 x 1 0 1 x 1 1 x' x 1 1 0 x 1 0 x' x 1 0 0 x 0 1 1 x com1 com2 1 1 0 x 1 1 1 x 1 1 0 x 1 1 x' x 1 1 0 x 1 0 x' x 1 1 1 x 1 1 x' x 0 1 0 x 1 1 1 x 1 0 x' x 1 1 0 x 1 1 0 x 0 1 0 x 1 0 x' x 1 1 1 x 0 0 x' x 1 0 0 x 1 1 1 x 0 1 x' x 1 1 0 x 0 0 0 x 0 0 x' x 1 0 0 x 1 1 1 x 0 1 x' x 1 1 0 x 0 0 0 x x' : any data because it is not connected to any segment on the lcd panel. x : any data because of tertiary time-sharing disply. lcd panel
m pd17201a, 17207 66 fig. 11-7 wiring example of quarternary time sharing lcd panel lcdd 0 (40 h) lcdd 1 (41 h) lcdd 2 (42 h) lcdd 3 (43 h) lcdd 4 (44 h) lcdd 5 (45 h) lcdd 6 (46 h) lcdd 7 (47 h) lcdd 8 (48 h) lcdd 9 (49 h) lcdd 10 (4 ah) lcdd 11 (4 bh) lcdd 12 (4 ch) lcdd 13 (4 dh) lcdd 14 (4 eh) lcdd 15 (4 fh) lcdd 16 (50 h) lcdd 17 (51 h) lcdd 18 (52 h) lcdd 19 (53 h) lcdd 20 (54 h) lcdd 21 (55 h) lcdd 22 (56 h) lcdd 23 (57 h) lcdd 24 (58 h) lcdd 25 (59 h) lcdd 26 (5 ah) lcdd 27 (5 bh) lcdd 28 (5 ch) lcdd 29 (5 dh) lcdd 30 (5 eh) lcdd 31 (5 fh) lcdd 32 (60 h) lcdd 33 (61 h) lcd0 lcd1 lcd3 lcd4 lcd5 lcd6 lcd7 lcd9 lcd10 lcd11 lcd12 lcd13 lcd14 lcd15 lcd16 lcd17 lcd18 lcd19 lcd20 lcd21 lcd22 lcd23 lcd24 lcd25 lcd26 lcd27 lcd28 lcd29 lcd30 lcd31 lcd32 lcd33 com0 bit0 bit1 bit2 bit3 1 1 1 0 1 1 1 1 1 0 1 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 1 0 com1 com2 0 1 1 0 0 1 0 1 1 0 1 0 1 1 0 0 0 1 1 1 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 com3 lcd2 lcd8 timing strobe lcd panel
m pd17201a, 17207 67 11.5 segment signals and common signals segment pins lcd 0 to lcd 35 are connected to the corresponding front electrodes of the lcd panel and common pins com 0 to com 3 are connected to corresponding rear electrodes of the lcd panel. the lcd panel lights when the potential difference between its segment and common signals goes beyond a preset voltage. the lcd panel is driven on an ac voltage because it degrades quickly if a dc voltage is continuously applied between its segment and common pins. figure 11-8 to fig. 11-10 shows waveforms of segment and common signals in each display mode. fig. 11-8 common and segment waveforms in each display mode (for lcden = 1) [mode 1] display mode [mode 2] [mode 3] v lcd2 com pin 0 com 1 pin com 2 pin com 3 pin lcd n pin com 0 -lcd n segment pin (lcd 25 ) segment pin (lcd 24 ) segment pin (lcd 24 ) v lcd1 v lcd0 gnd gnd gnd gnd gnd + v lcd2 + v lcd1 + v lcd0 gnd _ v lcd2 _ v lcd1 _ v lcd0 1 : the lcd stripe lights here (by an lcd selection voltage). 1 1 1 1 1 v lcd2 v lcd1 v lcd0 v lcd2 v lcd1 v lcd0 v lcd2 v lcd1 v lcd0 v lcd2 v lcd1 v lcd0
m pd17201a, 17207 68 fig. 11-9 common and segment waveforms for lcden = 0 (lcd display off) com 0 pin v lcd2 v lcd1 v lcd0 gnd gnd gnd gnd gnd + v lcd2 + v lcd1 + v lcd0 gnd _ v lcd0 _ v lcd1 _ v lcd2 com 1 pin com 2 pin com 3 pin lcd n pin com 0 -lcd n v lcd2 v lcd1 v lcd0 v lcd2 v lcd1 v lcd0 v lcd2 v lcd1 v lcd0 v lcd2 v lcd1 v lcd0
m pd17201a, 17207 69 fig. 11-10 common and segment waveforms for lcdmd0 = 0 and lcdmd1 = 0 (voltage booster circuit stop) com 0 pin v lcd2 v lcd1 v lcd0 gnd v lcd2 v lcd1 v lcd0 gnd v lcd2 v lcd1 v lcd0 gnd v lcd2 v lcd1 v lcd0 gnd v lcd2 v lcd1 v lcd0 gnd + v lcd2 + v lcd1 + v lcd0 gnd _ v lcd0 _ v lcd1 _ v lcd2 com 1 pin com 2 pin com 3 pin lcd n pin com 0 -lcd n
m pd17201a, 17207 70 11.6 voltage booster circuit for lcd driver the m pd17207 has a voltage booster circuit for lcd driver which prevents the lcd from flickering when the supply voltage fluctuates. output signals v lcd2 , v lcd1 , and v lcd0 of the segment and common signals are respectively two times (v lcd1 ), three times (v lcd2 ), and equal to the output (reference voltage, v lcd0 ) of the reference voltage generator. the reference voltage v lcd0 can be adjusted by a resistor connected to the reference voltage adjuster for lcd driver pin v lcdc . figure 11-11 shows an example of a circuit of adjusting the reference voltage for the lcd driver. figure 11-12 shows its operating principle. fig. 11-11 reference voltage adjusting circuit for lcd driver (example) caution when the power is switched on, the lcd may light until the supply voltage stabilizes because the voltages of the capacitors for the voltage regulator and driver are undefined. it is therefore recommended that the all-light mode be used immediately after the power is switched on. v lcd2 v lcd1 v lcd0 caph v lcdc capl pd17207 r1 r2 c2 c3 c4 c1 r1 + r2 = 2m w c1 = c2 = c3 = c4 = 0.47 f reference voltage v lcd0 can be adjusted by resistors r1 and r2. where v lcdc = 0.6 v, v lcd0 = r1 + r2 r2 v lcd1 = 2 v lcd0 (v) v lcd2 = 3 v lcd0 (v) 0.6 (v)
m pd17201a, 17207 71 fig. 11-12 operating principle of lcd driver voltage booster circuit (1) charge c1 with v lcd0 (v lcd0 ). (2) charge c3 with v lcd0 and voltage of c1 (v lcd0 + v lcd0 = 2 v lcd0 ). (1) through (3) are repeated to boost the voltage. ( ) indicates the logical value eventually reached. the voltage is not necessarily boosted to the level in ( ) at a time. (3) charge c4 with voltage of c3 and voltage of c1 (2 v lcd0 + v lcd0 = 3 v lcd0 ). caph capl c1 r1 r2 c2 c3 c4 regulator v lcd2 v lcd1 v lcd0 v dd v lcdc _ + v lcd0 caph capl c1 r1 r2 c2 c3 c4 regulator v lcd2 v lcd1 v lcd0 v dd v lcdc _ + v lcd0 2 v lcd0 caph capl c1 r1 r2 c2 c3 c4 regulator v lcd2 v lcd1 v lcd0 v dd v lcdc _ + v lcd0 3 v lcd0 2 v lcd0
m pd17201a, 17207 72 12. interrupt functions when a peripheral hardware unit (int pin, 8-bit timer, clock timer, or serial interface) makes an interrupt request, the interrupt function temporarily stops the execution of the current program and transfers program control to a predetermined address (termed a vector address). 12.1 interrupt sources the m pd17207 supports the four interrupt sources (see table 12-1). when accepting an interrupt, the m pd17207 automatically transfers program control to a predetermined address (called a vector address). table 12-1 vector addresses priority interrupt source vector address 1 8-bit timer (internal) 0004h 2 rising edge of int pin input (external) 0003h 3 clock timer (internal) 0002h 4 serial interface (internal) 0001h if two or more interrupt requests are issued at the same time, the interrupt requests are accepted according to the priorities assigned to them. accepting an interrupt is enabled or disabled by the ei or di instruction. basically, the interrupt is accepted when it is enabled by the ei instruction. while the di instruction is executed or while an interrupt is accepted, the other interrupts are disabled. to enable accepting another interrupt after one interrupt has been completed, the ei instruction must be executed before the reti instruction. the interrupt is accepted by the ei instruction after the instruction next to ei has been executed; therefore, no interrupt is accepted between the ei and reti instructions. 12.2 hardware of interrupt control circuit this section describes the flags of the interrupt control circuit. (1) interrupt request flag and interrupt enable flag the interrupt request flag (irqxxx) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is executed. an interrupt enable flag (ipxxx) is provided to each interrupt request flag. when the ipxxx flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled.
m pd17201a, 17207 73 (2) ei/di instruction whether an accepted interrupt is executed or not is specified by the ei or di instruction. when the ei instruction is executed, inte (interrupt enable flag), which enables the interrupt, is set to 1. the inte flag is not registered on the register file. consequently, the status of this flag cannot be checked by an instruction. the di flag clears the inte flag to 0 to disable all the interrupts. the inte flag is also cleared to 0 at reset, disabling all the interrupts. table 12-2 interrupt request flags and interrupt enable flags interrupt signal setting interrupt request flag interrupt request flag enable flag irq set when rising edge of int pin input signal is detected ip irqtm set by coincidence signal of 8-bit timer iptm set by interrupt request signal from watch timer. interrupt irqwtm request signal generation interval is selected by wtmmd flag ipwtm (rf: 03h, bit 2) irqsio set by signal indicating end of serial data transfer operation ipsio from serial interface 12.2.1 int flag this flag reads the status of the int pin. this flag is 1 when a high-level signal is on the int pin or 0 when a low-level signal is there. fig. 12-1 int flag bit 3 bit 2 bit 1 bit 0 000 i n t 000 r _ r: read _ : undefined read/write default at reset rf: address 0fh 0 1 int function int pin is low int pin is high
m pd17201a, 17207 74 12.2.2 interrupt enable flags these flags enable the corresponding interrupts to be accepted. 1: the interrupt is accepted. 2: the interrupt is not accepted. fig. 12-2 interrupt enable flags bit 3 bit 2 bit 1 bit 0 i p s i o 000 r/w 0 r: read, w: write read/write default at reset rf: address 2fh 0 1 iptm function disables interrupt by 8-bit timer enables interrupt by 8-bit timer i p w t m i p i p t m 0 1 ip disables interrupt by rising edge of int pin input enables interrupt by rising edge of int pin input 0 1 ipwtm disables interrupt by watch timer enables interrupt by watch timer 0 1 ipsio disables interrupt by serial interface enables interrupt by serial interface function function function
m pd17201a, 17207 75 12.2.3 interrupt request flags these flags indicates the occurrence or acceptance of the corresponding interrupt requests. 1: the interrupt request has been made. 0: the interrupt request has been accepted. it is possible to set the status of each interrupt request flag by programming. when you write 1 in an interrupt request flag, the corresponding interrupt can be generated by software. when you write 0 in an interrupt request flag, the corresponding interrupt being held is released. fig. 12-3 interrupt request flags (1/4) fig. 12-3 interrupt request flags (2/4) bit 3 bit 2 bit 1 bit 0 i r q s i o r/w 0 r 0 r 0 r 0 r: read, w: write read/write default at reset rf: address 3bh 0 1 irqsio function serial interface interrupt request has not been made. serial interface interrupt request has been made. 000 bit 3 bit 2 bit 1 bit 0 i r q w t m r 0 r/w 0 r 0 r 0 r: read, w: write read/write default at reset rf: address 3ch 0 1 irqwtm function watch timer interrupt request has not been made. watch timer interrupt request has been made. 000
m pd17201a, 17207 76 fig. 12-3 interrupt request flags (3/4) bit 3 bit 2 bit 1 bit 0 i r q r 0 r 0 r/w 0 r 0 r: read, w: write read/write default at reset rf: address 3dh 0 1 irq function interrupt request has not been made at rising edge of int pin input. interrupt request has been made at rising edge of int pin input. 0 00 fig. 12-3 interrupt request flags (4/4) note 1h even after the stop mode has been released. bit 3 bit 2 bit 1 bit 0 i r q t m r 0 r 0 r 0 r/w 1 note r: read, w: write read/write default at reset rf: address 3eh 0 1 irqtm function 8-bit timer interrupt request has not been made. 8-bit timer interrupt request has been made. 00 0
m pd17201a, 17207 77 12.3 interrupt sequence if the irqxx flag is set to 1 while the ipxx is 1, processing of an interrupt starts at the end of the instruction cycle of the instruction being executed when the irqxx flag was set. processing of an instruction made in the execution of an movt instruction starts at the end of the second instruction cycle as the movt instruction runs in the second instruction cycle. when the ipxx flag is 0, interrupt processing does not start until the ipxx flag is set even when the irqxx flag is set. when two or more interrupts are enabled, they are processed in the ascending order of priorities. (an interrupt must wait until processing of an interrupt of the higher priority ends.) 12.3.1 operations when interrupt is accepted when an interrupt has been accepted, the cpu performs processing in the following sequence: (1) decrements the value of the stack pointer (sp) by 1. (2) saves the current value of the program counter to the address stack register (asr) specified by the sp. if the branch (br) or subroutine call (call) instruction is executed when the interrupt has been accepted, the address of the program memory (rom) to which execution is to branch, or called is loaded to the pc. (3) saves the value of each flag (bcd, cmp, cy, z, ixe) of the bank register (bank) and program status word (psword) to the interrupt stack register (intsk, three levels). (4) transfers the vector address to the pc. one instruction cycle is required to perform the above processing. 12.3.2 returning from interrupt processing routine to return from an interrupt processing routine, use the reti instruction. then the following processing is executed within an instruction cycle. (1) restores the value of the interrupt stack register (intsk) to each flag (bcd, cmp, cy, z, ixe) of the program status word (psword). (2) restores the value of the address stack register (asr) specified by the stack pointer (sp) to the program counter. (3) increments the value of the stack pointer by 1. to accept another interrupt after an interrupt has been processed, it is necessary to execute an ei instruction before the reti instruction. an interrupt will never be accepted between the ei and reti instructions as an interrupt is accepted by the ei instruction only after the next instruction has been executed.
m pd17201a, 17207 78 13. standby functions the m pd17207 has two modes of standby functions: halt mode and stop mode. the standby functions reduce the power dissipation of the m pd17207. in halt mode, the m pd17207 stops the execution of the program with the main clock on. (the cpu stops to run.) this mode is kept until a halt releasing condition is satisfied. in stop mode, the m pd17207 stops the execution of the program with the main clock off. the m pd17207 dissipates less circuit current in stop mode than in halt mode. halt mode is set by the execution of a halt instruction and stop mode is set by the execution of a stop instruction. 13.1 halt mode in halt mode, the m pd17207 stops the execution of the program with the main clock on for reduction of its power dissipation. execute a halt instruction to set halt mode. the condition of releasing halt mode is determined by the operand of the halt instruction. see table 13-1. after halt mode is released, the m pd17207 performs operations as shown in table 13-2. caution do not execute an instruction to clear the interrupt request flag (irqxxx) whose interrupt enable flag (ipxxx) is set immediately before the halt 8h or halt 0ah instruction is executed. if the flag is cleared, the halt mode may not be set. table 13-1 halt mode releasing conditions operand value halt mode releasing condition 0010b 1) when an 8-bit timer interrupt request (irqtm) is made (02h) 1000b 1) when an interrupt request (irqtm, irqwtm, irqsio, or irq) is made for an interrupt (08h) whose enable flag (iptm, ipwtm, ipsio, or ip) is on (1) 2) when any of pins p0a 0 to p0a 3 goes low 1010b 1) when an 8-bit timer interrupt request (irqtm) is made (0ah) 2) when an interrupt request (irqwtm, irqsio, or irq) is made for an interrupt whose enable flag (ipwtm, ipsio, or ip) is on (1) others inhibited
m pd17201a, 17207 79 table 13-2 operations after halt mode has been released (a) halt 02h standby mode released by: interrupt enable status interrupt enable flag operation after release of standby mode satisfaction of release di disable execution starts from instruction following condition by interrupt enable halt request (irqtm) ei disable enable branches to vector address of interrupt (b) halt 08h standby mode released by: interrupt enable status interrupt enable flag operation after release of standby mode low level input to port 0a dont care dont care execution starts from instruction following halt satisfaction of release di disable standby mode is not released condition by interrupt enable execution starts from instruction following request (irqtm, irqwtm, halt irqsio, or irq) ei disable standby mode is not released enable branches to vector address of interrupt (c) halt 0ah standby mode released by: interrupt enable status interrupt enable flag operation after release of standby mode satisfaction of release di disable execution starts from instruction following condition by interrupt enable halt request (irqtm) ei disable enable branches to vector address of interrupt satisfaction of release di disable standby mode is not released condition by interrupt enable execution starts from instruction request (irqwtm, irqsio, following halt or irq) ei disable standby mode is not released enable branches to vector address of interrupt
m pd17201a, 17207 80 13.2 conditions of executing an halt instruction the halt instruction can be executed only under a specific condition for prevention of malfunction. see table 13-3. the halt instruction which does not satisfy the conditions listed in table 13-3 is treated as an nop instruction. table 13-3 conditions of executing the halt instruction operand value execution condition 0010b 1) the 8-bit timer interrupt request (irqtm) should be reset. (02h) 1) the interrupt request flag (irqtm, irqwtm, irqsio, or irq) should be reset for 1000b an interrupt whose enable flag (iptm, ipwtm, ipsio, or ip) is on (1) (08h) 2) all of pins p0a 0 to p0a 3 should be high input or output. 3) all of pins p0b 0 to p0b 3 should be in output mode and output latch should be 0. 1010b 1) the 8-bit timer interrupt request (irqtm) should be reset. (0ah) 2) the interrupt request flag (irqwtm, irqsio, or irq) should be reset for an interrupt whose enable flag (ipwtm, ipsio, or ip) is on (1) others reserved
m pd17201a, 17207 81 13.3 stop mode in stop mode, the m pd17207 stops the execution of the program with the main clock temporarily off for great reduction of its power dissipation. execute a stop instruction to set stop mode. the stop instruction is not valid for a system using a subclock only. when the system uses a subclock as the system clock (that is, when sysck = 0), the stop instruction is treated as an nop instruction. the condition of releasing stop mode is determined by the operand of the stop instruction. see table 13-4. after stop mode is released, the m pd17207 performs operations as follows: 1 clearing irqtm 2 starting watch timer and watchdog timer (not reset) 3 resetting and starting 8-bit timer 4 the instruction following stop 8h or the interrupt vector address is executed when the value of the 8-bit counter coincides with the value of the modulo register (setting of irqtm). caution when the subclock is used, the watch timer and watchdog timer do not stop even in the stop mode. the time interval between release of stop mode and start of the execution of the next instruction is set by the contents of the modulo register of the 8-bit timer. this time interval is expressed as follows: (tmm +1) x 1024/f x [sec] where, tmm : content of the modulo register f x : frequency of the main clock. example: in a system using the main clock of 4 mhz, the time interval between release of stop mode and start of the execution of the next instruction is: (tmm + 1) x 256 [microseconds] caution do not set an instruction that would clear the interrupt request flag (irqxxx) whose interrupt enable flag (ipxxx) is set immediately before the stop 8h instruction, if you set such an instruction, the stop mode may not be set. table 13-4 stop mode releasing conditions operand value stop mode releasing condition 1000b 1 when an interrupt request (irqwtm, irqsio, or irq) is made for an interrupt (08h) whose enable flag (ipwtm, ipsio, or ip) is on (1) 2 when any of pins p0a 0 to p0a 3 goes low others inhibited
m pd17201a, 17207 82 13.4 conditions of executing an halt instruction the stop instruction can be executed only under a specific condition for prevention of malfunction. see table 13-5. the stop instruction which does not satisfy the conditions listed in table 13-5 is treated as an nop instruction. table 13-5 conditions of executing the stop instruction operand value execution condition 1) the interrupt request flag should be reset for an interrupt whose enable flag 1000b (ipwtm, ipsio, or ip) is on (1) (08h) 2) all of pins p0a 0 to p0a 3 should be high input or output. 3) all of pins p0b 0 to p0b 3 should be in output mode and output latch should be 0. others inhibited fig. 13-1 releasing standby mode (a) releasing stop mode by interrupt remark the dotted line indicates when the interrupt that has released the standby mode is accepted (b) releasing halt mode by interrupt remark the dotted line indicates when the interrupt that has released the standby mode is accepted stop instruction wait (time set by tmm) halt mode oscillation operation mode stop mode oscillation stops operation mode oscillation standby release signal clock halt instruction oscillation operation mode halt mode operation mode standby release signal clock
m pd17201a, 17207 83 14. reset 14.1 reset by reset signal input when a low-level signal is input to the reset pin for 50 m s or more, the system is reset. the system must be reset at least once when the power is turned on, as the operation of the internal circuit is undefined. when reset has been effected, the following circuits are initialized: 1 the program counter is reset to 0. 2 the flags of the register file are initialized (for the initial values, refer to fig. 15-1 register file list). 3 initial value 0320h is written to the data buffer. 4 the peripheral hardware is initialized. 5 oscillation of the main clock is stopped. when the reset pin is made high, oscillation of the main clock is started, and about 64 ms after that (where the main clock frequency is 4 mhz), execution of the program is started from address 0. fig. 14-1 reset operation by reset input 14.2 reset by watchdog timer (reset and wdout pins connected) when the watchdog timer is activated while the program is being executed, a low level is output to the wdout pin, and the program counter is reset to 0. therefore, when the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0. when developing a program, reset the watchdog timer (set the wdtres flag) at intervals of 340 ms or less (where f x = 4 mhz). 14.3 reset by stack pointer (reset and wdout pins connected) when the value of the stack pointer reaches 6h or 7h while the program is being executed, a low level is output to the wdout pin, and the program counter is reset to 0. when the level of nesting of interrupt or subroutine call exceeds 5 (stack overflow), or when the return instruction is executed despite the stack level being 0 because the call instruction and return (ret) instruction have not been correctly used in pairs (stack underflow), the program can be restarted from address 0. wait (approx. 64 ms/4 mhz) starts from address 0 reset operation mode or standby mode main clock oscillation stopped halt mode operation mode
m pd17201a, 17207 84 table 14-1 hardware status after reset hardware reset input reset input in standby mode during operation program counter (pc) 0000h 0000h port i/o input input output latch 0 0 data memory (ram) general-purpose data memory holds previous status undefined (except dbf and port register) dbf 0320h 0320h system register (sysreg) 0 0 wr holds previous status undefined control register refer to fig. 15-1 register file list. 8-bit timer counter (tmc) 00h 00h modulo register (tmm) ffh ffh remote controller carrier nrz high-level period setting holds previous status undefined generator circuit modulo register (nrzhtmm) nrz low-level period setting modulo register (nrzltmm) counter of watch timer/watchdog timer 00h 00h shift register of serial interface (siosfr) holds previous status undefined internal reference voltage setting register of a/d converter (adcr) holds previous status undefined
m pd17201a, 17207 85 15. assembler reserved words 15.1 mask option directives in m pd17207 programming, it is required to specify mask options in assembler source programs by mask option directives. the following mask options items must be specified: ? pull-up resistor for the reset pin ? connection between the main clock and the subclock (for selection of system clock) 15.1.1 option and endop directives a mask option is defined in a block between the option and endop directives. this block is formatted as shown below. coding format: symbol mnemonic operand comment [label: ] option [;comment] : : : endop
m pd17201a, 17207 86 15.1.2 mask option definition pseudo directives table 15-1 shows directives available in the mask option definition block. table 15-1 mask option definition directives item directives number of 1st operand 2nd operands operands reset mask option reset pin resplup pull-up optres 1 (built-in pull-up resistor) resistor open (no pull-up resistor) main clock subclock usex usext (uses the main clock as uses the subclock as the system clock optck 2 the system clock.) system clock.) nox noxt (does not use the main (does not use the clock.) subclock.) remark when both the main clock and the subclock are specified as the system clock, the main clock is initially selected when the system is reset. after that, the subclock can be selected by an instruction in the program. shown below is a coding example of mask options. symbol mnemonic operand comment [label: ] option [;comment] optres resplup ; pulls up the reset pin. optck usex, usext ; uses the main clock or subclock. endop 15.2 reserved symbols table 15-2 lists the symbols defined by the device file of the m pd17207. the defined symbols include the following register file names, port names, and peripheral hardware names. 15.2.1 register file the symbol names assigned to the registers in the register file are defined. these registers are accessed via wr (window register) by the peek and poke instructions. fig. 15-1 lists the registers in the register file. 15.2.2 registers on data memory and ports the names of the registers assigned to data memory addresses 00h-7fh, ports assigned to address 70h and those that follow, and system registers are defined. fig. 15-2 shows the configuration of the data memory. 15.2.3 peripheral hardware the names of the peripheral hardware that is accessed by the get and put instructions are defined. table 15- 3 lists the peripheral hardware.
m pd17201a, 17207 87 table 15-2 list of reserved symbols (1/4) symbol name attribute value r/w description dbf3 mem 0.0ch r/w bit 15 to bit 12 of data buffer dbf2 mem 0.0dh r/w bit 11 to bit 8 of data buffer dbf1 mem 0.0eh r/w bit 7 to bit 4 of data buffer dbf0 mem 0.0fh r/w bit 3 to bit 0 of data buffer ar3 mem 0.74h r bit 15 to bit 12 of address register ar2 mem 0.75h r/w bit 11 to bit 8 of address register ar1 mem 0.76h r/w bit 7 to bit 4 of address register ar0 mem 0.77h r/w bit 3 to bit 0 of address register wr mem 0.78h r/w window register bank mem 0.79h r/w bank register ixh mem 0.7ah r/w bit 11 to bit 8 of index register mph mem 0.7ah r/w bit 7 to bit 4 of memory pointer mpe flg 0.7ah.3 r/w memory pointer enable flag ixm mem 0.7bh r/w bit 7 to bit 4 of index register mpl mem 0.7bh r/w bit 3 to bit 0 of memory pointer ixl mem 0.7ch r/w bit 3 to bit 0 of index register rph mem 0.7dh r/w bit 7 to bit 4 of register pointer rpl mem 0.7eh r/w bit 3 to bit 0 of register pointer psw mem 0.7fh r/w program status word bcd flg 0.7eh.0 r/w bcd operation flag cmp flg 0.7fh.3 r/w compare flag cy flg 0.7fh.2 r/w carry flag z flg 0.7fh.1 r/w zero flag ixe flg 0.7fh.0 r/w index register enable flag lcdd0 mem 0.40h r/w lcd segment 0 lcdd1 mem 0.41h r/w lcd segment 1 lcdd2 mem 0.42h r/w lcd segment 2 lcdd3 mem 0.43h r/w lcd segment 3 lcdd4 mem 0.44h r/w lcd segment 4 lcdd5 mem 0.45h r/w lcd segment 5 lcdd6 mem 0.46h r/w lcd segment 6 lcdd7 mem 0.47h r/w lcd segment 7 lcdd8 mem 0.48h r/w lcd segment 8 lcdd9 mem 0.49h r/w lcd segment 9 lcdd10 mem 0.4ah r/w lcd segment 10 lcdd11 mem 0.4bh r/w lcd segment 11 lcdd12 mem 0.4ch r/w lcd segment 12 lcdd13 mem 0.4dh r/w lcd segment 13 lcdd14 mem 0.4eh r/w lcd segment 14 lcdd15 mem 0.4fh r/w lcd segment 15
m pd17201a, 17207 88 table 15-2 list of reserved symbols (2/4) symbol name attribute value r/w description lcdd16 mem 0.50h r/w lcd segment 16 lcdd17 mem 0.51h r/w lcd segment 17 lcdd18 mem 0.52h r/w lcd segment 18 lcdd19 mem 0.53h r/w lcd segment 19 lcdd20 mem 0.54h r/w lcd segment 20 lcdd21 mem 0.55h r/w lcd segment 21 lcdd22 mem 0.56h r/w lcd segment 22 lcdd23 mem 0.57h r/w lcd segment 23 lcdd24 mem 0.58h r/w lcd segment 24 lcdd25 mem 0.59h r/w lcd segment 25 lcdd26 mem 0.5ah r/w lcd segment 26 lcdd27 mem 0.5bh r/w lcd segment 27 lcdd28 mem 0.5ch r/w lcd segment 28 lcdd29 mem 0.5dh r/w lcd segment 29 lcdd30 mem 0.5eh r/w lcd segment 30 lcdd31 mem 0.5fh r/w lcd segment 31 lcdd32 mem 0.60h r/w lcd segment 32 lcdd33 mem 0.61h r/w lcd segment 33 lcdd34 mem 0.62h r/w lcd segment 34 lcdd35 mem 0.63h r/w lcd segment 35 p0a0 flg 0.70h.0 r/w bit 0 of port 0a p0a1 flg 0.70h.1 r/w bit 1 of port 0a p0a2 flg 0.70h.2 r/w bit 2 of port 0a p0a3 flg 0.70h.3 r/w bit 3 of port 0a p0b0 flg 0.71h.0 r/w bit 0 of port 0b p0b1 flg 0.71h.1 r/w bit 1 of port 0b p0b2 flg 0.71h.2 r/w bit 2 of port 0b p0b3 flg 0.71h.3 r/w bit 3 of port 0b p0c0 flg 0.72h.0 r/w bit 0 of port 0c p0c1 flg 0.72h.1 r/w bit 1 of port 0c p0c2 flg 0.72h.2 r/w bit 2 of port 0c p0c3 flg 0.72h.3 r/w bit 3 of port 0c p0d0 flg 0.73h.0 r/w bit 0 of port 0d p0d1 flg 0.73h.1 r/w bit 1 of port 0d p0d2 flg 0.73h.2 r/w bit 2 of port 0d p0d3 flg 0.73h.3 r/w bit 3 of port 0d p1a0 flg 1.70h.0 r/w bit 0 of port 1a p1a1 flg 1.70h.1 r/w bit 1 of port 1a p1a2 flg 1.70h.2 r/w bit 2 of port 1a p1a3 flg 1.70h.3 r/w bit 3 of port 1a
m pd17201a, 17207 89 table 15-2 list of reserved symbols (3/4) symbol name attribute value r/w description sp mem 0.81h r/w stack pointer sysck flg 0.82h.1 r/w selection of system clock xen flg 0.82h.0 r/w main clock enable wdtres flg 0.83h.3 r/w watchdog timer reset wtmmd flg 0.83h.2 r/w selection of watch timer mode wtmres flg 0.83h.1 r/w reset of watch timer mode int flg 0.8fh.0 r int pin status nrzbf flg 0.91h.0 r/w nrz buffer data nrz flg 0.92h.0 r/w nrz data adccmp flg 0.0a0h.0 r/w comparator result vrefen flg 0.0a1h.3 r/w a/d converter enable flag adcen flg 0.0a1h.2 r/w a/d converter enable flag adcch1 flg 0.0a1h.1 r/w a/d converter channel selection flag adcch0 flg 0.0a1h.0 r/w a/d converter channel selection flag siots flg 0.0a2h.3 r/w serial interface start flag siohiz flg 0.0a2h.2 r/w so pin status siock1 flg 0.0a2h.1 r/w serial clock selection flag for serial interface siock0 flg 0.0a2h.0 r/w serial clock selection flag for serial interface nrzen flg 0.0a3h.2 r/w nrz enable flag tmoe flg 0.0a3h.1 r/w timer output enable flag sioen flg 0.0a3h.0 r/w sio enable flag p0dbio3 flg 0.0a7h.3 r/w i/o setting flag (bit 3 of port p0d) p0dbio2 flg 0.0a7h.2 r/w i/o setting flag (bit 2 of port p0d) p0dbio1 flg 0.0a7h.1 r/w i/o setting flag (bit 1 of port p0d) p0dbio0 flg 0.0a7h.0 r/w i/o setting flag (bit 0 of port p0d) ipsio flg 0.0afh.3 r/w intsio interrupt enable flag ipwtm flg 0.0afh.2 r/w watch timer interrupt enable flag ip flg 0.0afh.1 r/w interrupt enable flag iptm flg 0.0afh.0 r/w 8-bit timer interrupt enable flag lcden flg 0.0b1h.3 r/w lcd display enable flag lcdck2 flg 0.0b1h.2 r/w lcd display clock selection flag lcdck1 flg 0.0b1h.1 r/w lcd display clock selection flag lcdck0 flg 0.0b1h.0 r/w lcd display clock selection flag lcdmd3 flg 0.0b2h.3 r/w lcd display mode register bit 3 lcdmd2 flg 0.0b2h.2 r/w lcd display mode register bit 2 lcdmd1 flg 0.0b2h.1 r/w lcd display mode register bit 1 lcdmd0 flg 0.0b2h.0 r/w lcd display mode register bit 0 tmen flg 0.0b3h.3 r/w timer enable flag tmres flg 0.0b3h.2 r/w timer reset flag tmck1 flg 0.0b3h.1 r/w selection of timer clock source
m pd17201a, 17207 90 table 15-2 list of reserved symbols (4/4) symbol name attribute value r/w description tmck0 flg 0.0b3h.0 r/w selection of timer clock source p1agio flg 0.0b7h.3 r/w i/o setting flag for port 1a p0cgio flg 0.0b7h.2 r/w i/o setting flag for port 0c p0bgio flg 0.0b7h.1 r/w i/o setting flag for port 0b p0agio flg 0.0b7h.0 r/w i/o setting flag for port 0a irqsio flg 0.0bbh.3 r/w sio interrupt request flag irqwtm flg 0.0bch.2 r/w watch timer interrupt request flag irq flg 0.0bdh.1 r/w int interrupt request flag irqtm flg 0.0beh.0 r/w 8-bit timer interrupt request flag siosfr dat 01h r/w serial interface shift register tmm dat 02h w modulo register for 8-bit timer tmc dat 02h r counter register for 8-bit timer nrzhtmm dat 03h r/w modulo register for nrz low-level period nrzltmm dat 04h r/w modulo register for nrz high-level period adcr dat 05h r/w a/d converter internal reference voltage setting register ar dat 40h r/w peripheral address of address register for get/put/push/call/br/ movt/inc instruction
m pd17201a, 17207 91 [memo]
m pd17201a, 17207 92 fig. 15-1 register file (1/2) note status when the system is reset. * : when the mask option selects the main clock (usex): 1 when the mask option does not select the main clock (nox): 0 fig. 15-2 data memory configuration 0123456789abcdef dbf 0 1 2 3 4 5 6 7 row address column address dbf3 dbf2 dbf1 dbf0 ar3 ar2 ar1 ar0 wr bank ixh ixm ixl rph rpl psw system register p0d 0 - p0d 3 p0c 0 - p0c 3 p0b 0 - p0b 3 p0a 0 - p0a 3 p1a 0 - p1a 3 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 0 0 0 adccmp 0 0 0 0 nrzbf vrefen adcen adcch1 adcch0 lcden lcdck2 lcdck1 lcdck0 0 0 sysck xen 0 0 0 nrz siots siohiz siock1 siock0 lcdmd3 lcdmd2 lcdmd1 lcdmd0 wdtres wtmmd wtmres 0 0 nrzen tmoe sioen tmen tmres tmck1 tmck0 p0dbio3 p0dbio2 p0dbio1 p0dbio0 p1agio p0cgio p0bgio p0agio 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 note note note note note note note note 01234567 cdolumn address row address sp 0 (8) 1 (9) 2 (a) 3 (b)
m pd17201a, 17207 93 note status when the system is reset. p: when the int pin goes high: 1 when the int pin goes low: 0 remark ( ) indicates an address to be used when the assembler is used. all the flags of the control registers are registered to the device file as assembler reserved words. it is convenient to use these reserved words when you develop a program. table 15-3 peripheral hardware name address valid bit remarks siosfr 01h 8 shift register of serial interface tmc 02h 8 count register of 8-bit timer tmm 02h 8 modulo register of 8-bit timer nrzltmm 03h 8 low-level period setting modulo register for remote controller carrier generator nrzhtmm 04h 8 high-level period setting modulo register for remote controller carrier generator adcr 05h 8 compare voltage setting register of a/d converter ar 40h 16 address register fig. 15-1 register file (2/2) bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 irqsio 0 0 0 0 0 0 int ipsio ipwtm ip iptm 0 0 0 0 0 0 0 p 0 0 0 0 0 (8) note note note note note note note note 89abcdef cdolumn address row address 0 irqwtm 0 0 0 0 0 0 0 0 irq 0 0 0 0 0 0 0 0 irqtm 0 0 0 0 1 (9) 2 (a) 3 (b)
m pd17201a, 17207 94 16. instruction set 16.1 outline of instruction sets b 15 b 14 -b 11 01 bin hex 0000 0 add r, m add m, #n4 0001 1 sub r, m sub m, #n4 0010 2 addc r, m addc m, #n4 0011 3 subc r, m subc m, #n4 0100 4 and r, m and m, #n4 0101 5 xor r, m xor m, #n4 0110 6 or r, m or m, #n4 inc ar inc ix movt dbf, @ar br @ar call @ar ret retsk ei di 0111 7 reti push ar pop ar get dbf, p put p. dbf peek wr, rf poke rf, wr rorc r stop s halt h nop 1000 8 ld r, m st m, r 1001 9 ske m, #n4 skge m, #n4 1010 a mov @r, m mov m, @r 1011 b skne m, #n4 sklt m, #n4 1100 c br addr (page 0) call addr (page 0) 1101 d br addr (page 1) mov m, #n4 1110 e skt m, #n 1111 f skf m, #n
m pd17201a, 17207 95 16.2 legend ar : address register asr : address stack register specified by stack pointer addr : program memory address (lower 11 bits) bank : bank register cmp : compare flag cy : carry flag dbf : data buffer h : halt releasing condition intef : interrupt enable flag intr : register automatically saved to stack in case of interrupt intsk : interrupt stack register ix : index register mp : data memory row address pointer mpe : memory pointer enable flag m : data memory address specified by m r , m c m r : data memory row address (high) m c : data memory column address (low) n : bit position (4 bits) n4 : immediate data (4 bits) page : page (bit 11 of program counter) pc : program counter p : peripheral address p h : peripheral address (higher 3 bits) p l : peripheral address (lower 4 bits) r : general register column address rf : register file address rf r : register file address (higher 3 bits) rf c : register file address (lower 4 bits) sp : stack pointer s : stop releasing condition wr : window register ( ) : contents addressed by
m pd17201a, 17207 96 16.3 list of instruction sets group mnemonic operand operation instruction code op code operand add r, m (r) (r) + (m) 00000 m r m c r m, #n4 (m) (m) + n4 10000 m r m c n4 addition addc r, m (r) (r) + (m) + cy 00010 m r m c r m, #n4 (m) (m) + n4 + cy 10010 m r m c n4 inc ar ar ar +1 00111 000 1001 0000 ix ix ix +1 00111 000 1000 0000 sub r, m (r) (r) C (m) 00001 m r m c r subtraction m, #n4 (m) (m) C n4 10001 m r m c n4 subc r, m (r) (r) C (m) C cy 00011 m r m c r m, #n4 (m) (m) C n4 C cy 10011 m r m c n4 or r, m (r) (r) M (m) 00110 m r m c r m, #n4 (m) (m) M n4 10110 m r m c n4 logical and r, m (r) (r) ? (m) 00100 m r m c r m, #n4 (m) (m) ? n4 10100 m r m c n4 xor r, m (r) (r) " (m) 00101 m r m c r m, #n4 (m) (m) " n4 10101 m r m c n4 judge skt m, #n cmp 0, if (m) ? n = n, then skip 11110 m r m c n skf m, #n cmp 0, if (m) ? n = 0, then skip 11111 m r m c n ske m, #n4 (m)-n4, skip if zero 01001 m r m c n4 compare skne m, #n4 (m)-n4, skip if not zero 01011 m r m c n4 skge m, #n4 (m)-n4, skip if not borrow 11001 m r m c n4 sklt m, #n4 (m)-n4, skip if borrow 11011 m r m c n4 cy ? (r) b3 ? (r) b2 ? (r) b1 ? (r) b0 rotate rorc r 00111 000 0111 r ld r, m (r) (m) 01000 m r m c r st m, r (m) (r) 11000 m r m c r @r, m if mpe = 1 : (mp, (r)) (m) 01010 m r m c r if mpe = 0 : (bank, m r , (r)) (m) transfer mov m, @r if mpe = 1 : (m) (mp, (r)) 11010 m r m c r if mpe = 0 : (m) (bank, m r , (r)) m, #n4 (m) n4 11101 m r m c n4 movt note dbf, sp sp C 1, asr pc, pc ar 00111 000 0001 0000 @ar dbf (pc), pc asr, sp sp + 1 note two instruction cycles are necessary only for executing the movt instruction.
m pd17201a, 17207 97 group mnemonic operand operation instruction code op code operand push ar sp sp C 1, asr ar 00111 000 1101 0000 pop ar ar asr, sp sp +1 00111 000 1100 0000 transfer peek wr, rf wr (rf) 00111 rf r 0011 rf c poke rf, wr (rf) wr 00111 rf r 0010 rf c get dbf, p (dbf) (p) 00111 p h 1011 p l put p, dbf (p) (dbf) 00111 p h 1010 p l addr pc 10C0 addr, page 0 01100 addr branch br pc 10C0 addr, page 1 01101 @ar pc ar 00111 000 0100 0000 addr sp sp C 1, asr pc 11100 addr call pc 10C0 addr, page 0 @ar sp sp C 1, asr pc 00111 000 0101 0000 subroutine pc ar ret pc asr, sp sp +1 00111 000 1110 0000 retsk pc asr, sp sp +1 and skip 00111 001 1110 0000 reti pc asr, intr intsk, sp sp +1 00111 100 1110 0000 interrupt ei intef 1 00111 000 1111 0000 di intef 0 00111 001 1111 0000 stop s stop 00111 010 1111 s other halt h halt 00111 011 1111 h nop no operation 00111 100 1111 0000
m pd17201a, 17207 98 16.4 assembler (as17k) embedded macroinstructions legend flag n : flg symbol n : bit number < > : can be omitted mnemonic operand operation n embedded sktn flag 1, ... flag n if (flag 1) ~ (flag n) = all 1, then skip 1 n 4 macro skfn flag 1, ... flag n if (flag 1) ~ (flag n) = all 0, then skip 1 n 4 setn flag 1, ... flag n (flag 1) ~ (flag n) 11 n 4 clrn flag 1, ... flag n (flag 1) ~ (flag n) 01 n 4 notn flag 1, ... flag n if (flag n) = 0, then (flag n) 11 n 4 if (flag n) = 1, then (flag n) 0 initflg flag 1, ... if description = not flag n, then (flag n) 01 n 4 < flag n> if description = flag n, then (flag n) 1 bankn (bank) n0 n 2
m pd17201a, 17207 99 17. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test condition rating unit supply voltage v dd C0.3 to+7.0 v analog supply voltage v adc C0.3 to v dd +0.3 v input voltage v i C0.3 to v dd +0.3 v output voltage v o C0.3 to v dd +0.3 v rem pin peak value C30 ma effective value C20 ma high-level output current i oh one pin (except rem) peak value C7.5 ma effective value C5 ma all pins (except rem) peak value C22.5 ma effective value C15 ma one pin peak value 7.5 ma low-level output current i ol effective value 5 ma all pins (except rem) peak value 22.5 ma effective value 15 ma operating ambient temperature t a C20 to +75 c storage temperature t stg C40 to +125 c note effective value = peak value x duty caution even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. the absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. be sure not to exceed or fall below this value when using the product. capacitance (t a = 25 c, v dd = 0 v) parameter symbol test condition min. typ. max. unit input capacitance c in int, si, and reset pins 10 pf
m pd17201a, 17207 100 recommended operating ranges (t a = C20 to +75 c) parameter symbol test condition min. typ. max. unit v dd1 system clock f x = 4 mhz 2.2 3.0 5.5 v supply voltage v dd2 system clock f x = 8 mhz 4.5 5.0 5.5 v v dd3 system clock f xt = 32.768 khz 2.0 3.0 5.5 v main clock oscillation frequency f x 1.0 4 8.0 mhz subclock oscillation frequency f xt 32.768 khz 10 9 8 7 6 5 4 3 2 1 0.5 023456(v) (mhz) supply voltage (v dd ) f x vs v dd main system clock (f x ) guaranteed operation range 2.2 4.5 5.5
m pd17201a, 17207 101 main system clock oscillator characteristics (t a = C20 to +75 c, v dd = 2.2 to 5.5 v) resonator recommended item conditions min. typ. max. unit constants 1.0 4 8.0 mhz from when v dd reaches the minimum oscillation 4 ms voltage 1.0 4 8.0 mhz v dd = 4.5 to 5.5v 10 ms 30 ms notes 1. the oscillation frequency is indicated only to express the oscillator characteristics. 2. the oscillation stabilization time is the time required for stabilizing the oscillation after v dd is applied or the stop mode is released. 3. the recommended oscillators are shown in the table described later. subsystem clock oscillator characteristics resonator recommended item conditions min. typ. max. unit constants 32.768 khz 510s caution when using the main system clock and the subsystem clock generators, in order to avoid wiring capacitance effects, the following notations must be read and observed for wiring the portion inside the dotted line in the table: ? wiring length must be minimized. ? do not cross with other signal lines. do not wire close to a large current line. ? capacitors used in the oscillators must always be grounded to gnd potential level. never ground the grounding pattern having a large current flow. ? do not take the signal directly out of the oscillator. in order to reduce the power consumption, the subsystem clock oscillator employs a low amplification factor circuit. because of this, the subsystem clock oscillator is more sensitive to noise than the main system clock oscillator. therefore, when using the subsystem clock, wiring must be carefully planned. ceramic note 3 oscillator crystal note 3 oscillator oscillation frequency (fx) note 1 oscillation stabilization time note 2 oscillation frequency (f x ) note 1 oscillation stabilization time note 2 crystal oscillator oscillation stabilization time oscillation frequency (f xt ) x in x out c2 c1 x in x out c2 c1 x in x out
m pd17201a, 17207 102 recommended oscillators main system clock oscillator (made of ceramic) external capacitance oscillation voltage range manufacturer part name (pf) (v) remarks c1 c2 min. max. csa3.58mg 30 30 2.0 6.0 csa4.00mg 30 30 2.0 6.0 csa4.19mg 30 30 2.0 6.0 murata mfg. cst3.58mgw not required not required 2.0 6.0 cst4.00mgw not required not required 2.0 6.0 built-in capacitor cst4.19mgw not required not required 2.0 6.0 kbr3.58ms 33 33 2.0 6.0 kyocera kbr4.0ms 33 33 2.0 6.0 kbr4.19ms 33 33 2.0 6.0 toko crhf4.00 18 18 2.0 6.0 daishinku prs0400bcsan 39 33 2.0 6.0 main system clock oscillator (made of crystal) external capacitance oscillation voltage range manufacturer frequency holder (pf) (v) remarks (mhz) c1 c2 min. max. kinseki 4.0 hc-49u-s 22 22 2.0 6.0
m pd17201a, 17207 103 x not installed or stop mode xt installed (f xt =32.768 khz) dc characteristics (t a = C20 to +75 c, v dd = v adc = 2.2 to 3.6 v) parameter symbol test condition min. typ. max. unit high-level input voltage v ih1 reset and int pins 0.8v dd v dd v v ih2 other than reset and int pins 0.7v dd v dd v low-level input voltage v il1 reset and int pins 0 0.2v dd v v il2 other than reset and int pins 0 0.3v dd v high-level input leakage current i lih1 xt in , xt out , x in , and x out pins 20 m a i lih2 other than xt in , xt out , x in , and x out pins 3 m a low-level input leakage current i lil1 xt in , xt out , x in , and x out pins C20 m a i lil2 other than xt in , xt out , x in , and x out pins C3 m a high-level output current i oh1 rem pin v oh =v dd -1.2 v C7 C15 ma i oh2 note 1 v oh =v dd -0.3 v C0.3 C0.7 ma low-level output current i ol note 2 v ol =0.3 v 0.5 0.9 ma built-in pull-up resistor r p0a p0a 0 to p0a 3 pins 100 200 350 k w r res reset pins (mask option) 24 47 94 k w a/d absolute precision 2 lsb a/d resolution 8 bits a/d converter circuit current i adc 60 120 m a comparator error in comparator mode 10 20 mv i dd1 x installed (fx=4.19 mhz) run mode 0.8 2.0 ma i dd2 xt not installed halt mode 0.3 1.5 ma supply current i dd3 v dd =3 v stop mode 2.0 10 m a i dd4 run mode 7.0 25 m a i dd5 note 3 v dd =3 v halt mode 3.0 15 m a notes 1. p0a 0 to p0a 3 , p0d 0 to p0d 3 , and p1a 0 to p1a 2 pins 2. p0a 0 to p0a 3 , p0b 0 to p0b 3 , p0c 0 to p0c 3 , p0d 0 to p0d 3 , p1a 0 to p1a 2 , wdout, and rem pins 3. the specifications of the main stop mode (sub-mounting) are the same as the sub-halt mode (with the main clock oscillation stopped). lcd characteristics (t a = C20 to +75 c, v dd = 2.2 to 3.6 v) parameter symbol test condition min. typ. max. unit v lcdc output voltage v lcdc v dd = 3 v, t a = 25 c, r1 = r2 = 1 m w 0.5 0.6 0.7 v lcd reference output voltage v lcd0 external variable resistance 0.8 1.8 v (0 to 2.2 m w ) doubler output voltage v lcd1 c1 to c4 = 0.47 m f 1.9 2.0 v lcd0 tripler output voltage v lcd2 c1 to c4 = 0.47 m f 2.85 3.0 v lcd0 lcd common output current i com output voltage deviation = 0.2 v 30 m a lcd segment output current i lcd output voltage deviation = 0.2 v 5 m a
m pd17201a, 17207 104 dc characteristics (t a = C20 to +75 c, v dd = v adc = 5 v 10%) parameter symbol test condition min. typ. max. unit high-level input voltage v ih1 reset and int pins 0.8v dd v dd v v ih2 other than reset and int pins 0.7v dd v dd v low-level input voltage v il1 reset and int pins 0 0.2v dd v v il2 other than reset and int pins 0 0.3v dd v high-level input leakage current i lih1 xt in , xt out , x in , and x out pins 20 m a i lih2 other than xt in , xt out , x in , and x out pins 3 m a low-level input leakage current i lil1 xt in , xt out , x in , and x out pins C20 m a i lil2 other than xt in , xt out , x in , and x out pins C3 m a high-level output current i oh1 rem pin v oh = v dd -0.6 v C7 C15 ma i oh2 note 1 v oh = v dd -0.3 v C0.8 C1.2 ma low-level output current i ol note 2 v ol = 0.3 v 1.0 1.5 ma built-in pull-up resistor r p0a p0a 0 to p0a 3 pins 140 200 350 k w r res reset pins (mask option) 27 47 94 k w a/d absolute precision 2 lsb a/d resolution 8 bits a/d converter circuit current i adc 60 120 m a comparator error in comparator mode 10 20 mv i dd1 x installed (fx=4.19 mhz) run mode 1.8 5.0 ma i dd2 xt not installed halt mode 0.6 2.0 ma supply current i dd3 v dd = 5 v stop mode 2.6 20 m a i dd4 run mode 10.5 40 m a i dd5 v dd = 5 v halt mode 6.0 20 m a notes 1. p0a 0 to p0a 3 , p0d 0 to p0d 3 , and p1a 0 to p1a 2 pins 2. p0a 0 to p0a 3 , p0b 0 to p0b 3 , p0c 0 to p0c 3 , p0d 0 to p0d 3 , p1a 0 to p1a 2 , rem, and wdout pins 3. the specifications of the main stop mode (sub-mounting) are the same as the sub-halt mode (with the main clock oscillation stopped). lcd characteristics (t a = C20 to +75 c, v dd = 5 v 10%) parameter symbol test condition min. typ. max. unit lcd reference output voltage v lcd0 external variable resistance 0.8 1.8 v (0 to 2.2 m w ) doubler output voltage v lcd1 c1 to c4 = 0.47 m f 1.9 2.0 v lcd0 tripler output voltage v lcd2 c1 to c4 = 0.47 m f 2.85 3.0 v lcd0 lcd common output current i com output voltage deviation = 0.2 v 30 m a lcd segment output current i lcd output voltage deviation = 0.2 v 5 m a x not installed or stop mode xt installed (f x = 32.768 khz)
m pd17201a, 17207 105 ac characteristics (t a = C20 to +75 c, v dd = 2.2 to 5.5 v) parameter symbol test condition min. typ. max. unit v dd =5 v 10 % data input 2.0 m s sck input cycle time t kcy data output 10 m s data input 5 m s data output 13 m s v dd =5 v 10 % data input 1.0 m s sck input high- and low-level t kh , data output 5.0 m s widths t kl data input 2.5 m s data output 6.5 m s si setup time (vs. sck )t sik 100 ns si hold time (vs. sck )t ksi 100 ns sck ?? to so output delay time t kso c l =100 pf 4.5 m s int high- and low-level width t ioh , 50 m s t iol reset low-level width t rsl 50 m s p0a low-level width t rlsl standby release 10 m s serial transfer timing 3-line serial i/o mode sck si so input data output data t kcy t kl t kh t ksi t sik t kso
m pd17201a, 17207 106 18. performance curve (reference value) 4.0 3.0 2.0 (t a = 25 ? c) i dd1 vs v dd x in x out xt in xt out ceramic oscillator crystal resonator 32.768 khz 1.0 f x = 8 mhz operation mode f x = 4 mhz operation mode 0 1.0 2.2 2.0 3.0 4.0 5.0 6.0 5.5 operating supply current i dd1 (ma) f x = 2 mhz operation mode f x = 8 mhz halt mode f x = 4 mhz halt mode f x = 2 mhz halt mode supply voltage v dd (v)
m pd17201a, 17207 107 (t a = 25 ? c) (t a = 25 ? c) i dd1 vs f x (operation mode) operating supply current i dd1 (ma) 4.0 3.0 2.0 1.0 0 v dd = 5.0 v v dd = 4.0 v v dd = 3.0 v v dd = 2.5 v 012 4 8 f x (mhz) i dd2 vs f x (halt mode) 3.0 halt current i dd2 (ma) v dd = 5.0 v v dd = 4.0 v v dd = 3.0 v v dd = 2.5 v 2.0 1.0 0 012 4 8 f x (mhz)
m pd17201a, 17207 108 (t a = 25 ? c) (t a = 25 ? c) v dd -v oh (v) i oh1 (rem) vs v dd -v oh i oh2 (p0a) vs v dd -v oh _ 40 _ 30 _ 20 _ 10 012345 v dd -v oh (v) 012345 _ 40 _ 30 _ 20 _ 10 high-level output current i oh1 (rem) (ma) high-level output current i oh2 (p0a) (ma) v dd = 5 v v dd = 4 v v dd = 3 v v dd = 5 v v dd = 4 v v dd = 3 v (t a = 25 ? c) i oh2 (p1a) vs v dd -v oh _ 40 _ 30 _ 20 _ 10 high-level output current i oh2 (p1a) (ma) v dd = 5 v v dd = 4 v v dd = 3 v v dd -v oh (v) 012345
m pd17201a, 17207 109 (t a = 25 ? c) (t a = 25 ? c) (t a = 25 ? c) (t a = 25 ? c) i ol (rem) vs v ol i ol (p0a) vs v ol low-level output current i ol (rem) (ma) 40 30 20 10 012 345 low level output voltage v ol (v) 012 345 low level output voltage v ol (v) low-level output current i ol (p0a) (ma) 40 30 20 10 v dd = 5 v v dd = 4 v v dd = 3 v v dd = 5 v v dd = 4 v v dd = 3 v i ol (p0b) vs v ol i ol (p1a) vs v ol low-level output current i ol (p0b) (ma) 40 30 20 10 low-level output current i ol (p1a) (ma) 40 30 20 10 v dd = 5 v v dd = 4 v v dd = 3 v v dd = 5 v v dd = 4 v v dd = 3 v 012 345 low level output voltage v ol (v) 012 345 low level output voltage v ol (v)
m pd17201a, 17207 110 19. example of application circuit ? remote controller for air conditioner 0.47 f m 2 mw 32 khz 0.1 f m 0.1 f m 0.47 f m 0.47 f m 0.47 f m 80 lcd rem int pd17207gf ?be m 4 mhz 3 v v dd slide sw led key matrix standby mode release keys option sw input v dd temperature sensor v adc adc 0 adc 1 adc 2 sensor error detection humidity sensor 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
m pd17201a, 17207 111 20. package drawings package drawings of mass-production product caution the es and mass-production products differ in external shape and materials. please refer to the package drawing for the es product. item millimeters inches g q f 1.8 0.1250.075 1.0 s 0.031 0.0050.003 0.039 s80gf-80-3b9-3 note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 3.0 max. 0.119 max. d 17.20.2 0.6770.008 r5 5 5 5 b 20.00.2 0.787 +0.009 C0.008 a 23.20.2 0.913 +0.009 C0.008 80 pin plastic qfp (14 20) c 14.0?.2 0.551 +0.009 ?.008 j 0.8 (t.p.) 0.031 (t.p.) i 0.15 0.006 h 0.35?.10 0.014 +0.004 ?.005 p 2.7 0.106 n 0.10 0.004 l 0.8?.2 0.031 +0.009 ?.008 m 0.15 0.006 +0.004 ?.003 k 1.6?.2 0.063?.008 +0.10 ?.05 detail of lead end m 64 65 40 80 1 25 24 41 a b c d f g h i j k m l n p s q r
m pd17201a, 17207 112 20.0 18.4 64 41 24 1 0.8 0.32 0.15 12.0 14.2 2.25 bottom es product package drawings es 80-pin ceramic qfp (for reference) (unit: mm) caution 1. the metal cap is connected to pin 33 and is at the gnd level. 2. leads on the bottom of the package are guided slantingly. 3. package length does not include end flash burr.
m pd17201a, 17207 113 21. recommended soldering conditions for the m pd17207, soldering must be performed under the following conditions. for details of recommended conditions for surface mounting, refer to information document semiconductor device mounting technology manual (c10535e). for other soldering methods, please consult with nec personnel. table 21-1 soldering conditions of surface mount type m pd17201agf-xxx-3b9: 80-pin plastic qfp (14 20 mm) m pd17207gf-xxx-3b9: 80-pin plastic qfp (14 20 mm) soldering method soldering conditions symbol infrared reflow ir35-207-2 vps vp15-207-2 wave soldering ws60-207-1 partial heating pin temperature: 300 o c max., time: 3 seconds max. (per side of device) note the number of days the device can be stored after the dry pack was opened, under storage conditions of 25 o c and 65% rh max. caution do not use two or more soldering methods in combination (except the partial heating method). package peak temperature: 235 o c, time: 30 seconds max. (210 o c min.), number of times: 2 max., days: 7 days note (after that, prebaking is necessary for 20 hours at 125 o c) cannot be baked while packed in anything other than a heat-resistant tray (i.e. magazine, taping or non-heat resistant tray). package peak temperature: 215 o c, time: 40 seconds max. (200 o c min.), number of times: 2 max., days: 7 days note (after that, prebaking is necessary for 20 hours at 125 o c) cannot be baked while packed in anything other than a heat-resistant tray (i.e. magazine, taping or non-heat resistant tray). solder bath temperature: 260 o c max., time: 10 seconds max. number of times: 1, pre-heating temperature: 120 c max. (package surface tempera- ture), days: 7 days note (after that, prebaking is necessary for 20 hours at 125 c)
m pd17201a, 17207 114 appendix a. differences between m pd17p207 and m pd17201a/17207 the m pd17p207 has a prom to which the user can write a program in place of the internal mask rom of the m pd17201a and 17207. therefore, the m pd17p207 is identical to m pd17201a and 17207 except for the program memory and mask option. however, some of the electrical characteristics, such as supply current and v lcd0 voltage of the m pd17p207, are different from that of the m pd17201a and 17207 . the following table lists the differences between the m pd17p207 and m pd17201a/17207. item m pd17p207 m pd17p207 m pd17p207 m pd17201a m pd17207 product name C001 C002 C003 one-time prom mask rom program memory 0000h-0fffh 0000h-0bffh 0000h-0fffh 4096 16 bits 3072 16 bits 4096 16 bits pull-up resistor of reset pin not provided not provided main clock oscillator circuit provided provided any (mask option) subclock oscillator circuit not provided provided v pp pin, prom program pin provided not provided supply voltage v dd = 2.5 to 5.5 v (at f x = 4 mhz) (t a = C20 to +75 c) v dd = 2.4 to 5.5 v (at f x = 4 mhz, v dd = 2.2 to 5.5 v (at f x = 4 mhz) t a = C20 to +60 c) package 80-pin plastic qfp (14 20 mm) caution when using the m pd17p207-001, be sure to connect an oscillator to both the main clock oscillation circuit and subclock oscillation circuit.
m pd17201a, 17207 115 ? ? appendix b. functional comparison of m pd17201a/17207 related products product name m pd17201a m pd17207 m pd17215 m pd17216 m pd17217 m pd17218 item rom capacity (bits) 3072 16 4096 16 2048 16 4096 16 6144 16 8192 16 ram capacity (bits) 336 4 111 4 233 4 lcd controller/drive 136 segments max. not provided infrared remote controller carrier led output is high-active internal (no led output) generator (rem) i/o ports 19 lines 20 lines external interrupt (int) 1 line (rising-edge detection) 1 line (rising-edge, falling-edge detection) analog input 4 channels (8-bit a/d) not provided timer 2 channels 8-bit timer 2 channels 8-bit timer watch timer basic interval timer watchdog timer internal (wdout output) low-voltage detection circuit not provided internal (wdout output) serial interface 1 channel not provided stack 5 levels (3 levels for multiplexed interrupt) 4 m s (4 mhz: with ceramic ? 2 m s (8 mhz ceramic oscilator: in high-speed mode) instruction main system clock or crystal oscillator) ? 4 m s (4 mhz ceramic oscilator: in high-speed mode) execution time ? 16 m s (1 mhz ceramic oscilator: in high-speed mode) subsystem clock 488 m s (32.768 khz: not provided with crystal oscillator) supply voltage main system clock 2.2 to 5.5 v (at f x = 4 mhz) 2.2 to 5.5 v (at f x = 4 mhz, in high speed) subsystem clock 2.0 to 5.5 v (at f xt = 32.768 khz) not provided standby function stop, halt pakcage 80-pin plastic qfp 28-pin plastic sop 28-pin plastic shrink dip one-time prom product m pd17p207 m pd17p218 caution the electrical characteristics differ between the mask rom model and one-time prom model.
m pd17201a, 17207 116 appendix c. development tools the following tools are available for development of m pd17207 progams: hardware name outline the ie-17k, ie-17k-et, and emu-17k are in-circuit emulators that can be commonly used with the 17k series products. the ie-17k and ie-17k-et are connected to the host machine, which is a pc-9800 series product or ibm pc/at tm , via rs-232-c. the emu-17k is inserted into an expansion slot of a pc-9800 series product. when these in-circuit emulators are used in combination with a system evaluation board (se board) dedicated to each model of the device, they operate as the emulator dedicated to that model. a more sophisticated debugging environment can be created by using the man-machine interface software, simplehost tm . the emu-17k has a function that allows you to check the contents of the data memory real- time. se board (se-17207) the se-17207 is an se board for the m pd17201a, 17207, and 17p207. it may be used alone to evaluate a system, or in combination with an in-circuit emulator for debugging. emulation probe the ep-17201gf is an emulation probe for the m pd17201a, 17207, and 17p207. (ep-17201gf) it connects an se board and the target system. conversion socket the ev-9200g-80 is a socket for an 80-pin qfp (14 x 20 mm) and connects the ep- (ev-9200g-80 note 3 ) 17201gf and the target system. the af9703, af9704, af9705, and af9706 are prom programmers that can program the m pd17p207. when connected with programmer adapter af-9808a, this prom programmer can program the m pd17p207. program adapter the af-9808a is an adapter for programming the m pd17p207 and is used in (af-9808a note 4 ) combination with the af-9703, af-9704, af-9705 and af-9706. notes 1. low-cost model: external power supply type 2. this is a product from i.c corp. for details, consult i.c corp. 3. two ev-9200g-80s are supplied with the ep-17201gf. five ev-9200g-80s are optionally available as a set. 4. these are products from ando electric co., ltd. for details, consult ando electric. prom programmer (af-9703 note 4 , af-9704 note 4 af-9705 note 4 , af-9706 note 4 ) in-circuit emulators ie-17k ie-17k-et note 1 emu-17k note 2
m pd17201a, 17207 117 software name outline machine host os media supply order code pc-9800 series ms-dos tm 5" 2hd m s5a10as17k 3.5" 2hd m s5a13as17k ibm pc/at pc dos tm 5" 2hc m s7b10as17k 3.5" 2hc m s7b13as17k pc-9800 series ms-dos 5" 2hd m s5a10as17201 3.5" 2hd m s5a13as17201 ibm pc/at pc dos 5" 2hc m s7b10as17201 3.5" 2hc m s7b13as17201 pc-9800 series ms-dos 5" 2hd m s5a10as17207 3.5" 2hd m s5a13as17207 ibm pc/at pc dos 5" 2hc m s7b10as17207 3.5" 2hc m s7b13as17207 pc-9800 series ms-dos 5" 2hd m s5a10ie17k windows 3.5" 2hd m s5a13ie17k ibm pc/at pc dos 5" 2hc m s7b10ie17k 3.5" 2hc m s7b13ie17k remark the corresponding os versions are as follows: os version ms-dos ver. 3.30 to ver. 5.00a note pc dos ver. 3.1 to ver. 5.0 note windows ver. 3.0 to ver. 3.1 note ver. 5.00/5.00a of ms-dos and ver. 5.0 of pc dos have a task swap function, but this function cannot be used with this software. as17k is an assembler in common with the 17k series products. when developing the program of the m pd17201a and the m pd17207, as17k is used in combination with a device file (as17201a, as17207). as17201 is a device file for m pd17201a, and it is used in combi- nation with an assembler for the 17k series (as17k) as17207 is a device file for m pd17207, and it is used in combination with an assembler for the 17k series (as17k). simplehost is a software package that enables man-machine interface on the windows tm when a program is developed by using an incircuit emulator and a personal computer. 17k series assembler (as17k) device file (as17201) device file (as17207) support software ( simplehost )
m pd17201a, 17207 118 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd17201a, 17207 119 nec electronics inc. (u.s.) mountain view, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby sweden tel: 8-63 80 820 fax: 8-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 3
no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. simplehost is a trademark of nec corporation ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. m pd17201a, 17207

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